forked from OSchip/llvm-project
[VE] Add SVOB intrinsic instruction
Add SVOB intrinsic instruction and a regression test. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94279
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// Define intrinsics written by hand
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// Define intrinsics written by hand
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// VEL Intrinsic instructions.
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let TargetPrefix = "ve" in {
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def int_ve_vl_svob : GCCBuiltin<"__builtin_ve_vl_svob">,
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Intrinsic<[], [], [IntrHasSideEffects]>;
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}
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// Define intrinsics automatically generated
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// Define intrinsics automatically generated
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include "llvm/IR/IntrinsicsVEVL.gen.td"
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include "llvm/IR/IntrinsicsVEVL.gen.td"
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// Define intrinsics written by hand
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// Define intrinsics written by hand
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// SVOB pattern.
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def : Pat<(int_ve_vl_svob), (SVOB)>;
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// The lsv and lvs patterns
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// The lsv and lvs patterns
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def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
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def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
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(LSVrr_v (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, sub_i32),
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(LSVrr_v (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, sub_i32),
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test set vector out-of-order memory access boundary intrinsic instructions
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;;;
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;;; Note:
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;;; We test SVOB instruction.
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; Function Attrs: nounwind
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define fastcc void @svob_svob() {
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; CHECK-LABEL: svob_svob:
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; CHECK: # %bb.0:
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; CHECK-NEXT: svob
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; CHECK-NEXT: b.l.t (, %s10)
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tail call void @llvm.ve.vl.svob()
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.ve.vl.svob()
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