forked from OSchip/llvm-project
parent
d01efb547f
commit
120ad01fcb
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@ -6238,6 +6238,7 @@ X86TargetLowering::getConstraintType(const std::string &Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'A':
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case 'f':
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case 'r':
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case 'R':
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case 'l':
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@ -6399,6 +6400,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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else if (VT == MVT::i8)
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return std::make_pair(0U, X86::GR8RegisterClass);
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break;
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case 'f': // FP Stack registers.
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// If SSE is enabled for this VT, use f80 to ensure the isel moves the
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// value to the correct fpstack register class.
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if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
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return std::make_pair(0U, X86::RFP32RegisterClass);
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if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
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return std::make_pair(0U, X86::RFP64RegisterClass);
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return std::make_pair(0U, X86::RFP80RegisterClass);
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case 'y': // MMX_REGS if MMX allowed.
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if (!Subtarget->hasMMX()) break;
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return std::make_pair(0U, X86::VR64RegisterClass);
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