forked from OSchip/llvm-project
[ARM] Ensure CountReg definition dominates InsertPt when creating t2DoLoopStartTP
Of course there was something missing, in this case a check that the def of the count register we are adding to a t2DoLoopStartTP would dominate the insertion point. In the future, when we remove some of these COPY's in between, the t2DoLoopStartTP will always become the last instruction in the block, preventing this from happening. In the meantime we need to check they are created in a sensible order. Differential Revision: https://reviews.llvm.org/D91287
This commit is contained in:
David Green
parent
ec63dfe368
commit
11dee2eae2
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@ -230,6 +230,11 @@ bool MVEVPTOptimisations::ConvertTailPredLoop(MachineLoop *ML,
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if ((InsertPt != MBB->end() && !DT->dominates(&*InsertPt, &Use)) ||
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if ((InsertPt != MBB->end() && !DT->dominates(&*InsertPt, &Use)) ||
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!DT->dominates(ML->getHeader(), Use.getParent()))
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!DT->dominates(ML->getHeader(), Use.getParent()))
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InsertPt = &Use;
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InsertPt = &Use;
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if (InsertPt != MBB->end() &&
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!DT->dominates(MRI->getVRegDef(CountReg), &*InsertPt)) {
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LLVM_DEBUG(dbgs() << " InsertPt does not dominate CountReg!\n");
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return false;
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}
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MachineInstrBuilder MI = BuildMI(*MBB, InsertPt, LoopStart->getDebugLoc(),
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MachineInstrBuilder MI = BuildMI(*MBB, InsertPt, LoopStart->getDebugLoc(),
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TII->get(ARM::t2DoLoopStartTP))
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TII->get(ARM::t2DoLoopStartTP))
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@ -0,0 +1,214 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+lob -run-pass=arm-mve-vpt-opts %s -verify-machineinstrs -o - | FileCheck %s
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--- |
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define i32 @test(i16* nocapture readonly %x, i16* nocapture readonly %y, i32 %n) {
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entry:
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%cmp10 = icmp sgt i32 %n, 0
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%0 = add i32 %n, 7
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%1 = lshr i32 %0, 3
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%2 = shl nuw i32 %1, 3
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%3 = add i32 %2, -8
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%4 = lshr i32 %3, 3
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%5 = add nuw nsw i32 %4, 1
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br i1 %cmp10, label %vector.ph, label %for.cond.cleanup
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vector.ph: ; preds = %entry
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%6 = call i32 @llvm.start.loop.iterations.i32(i32 %5)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv3 = phi i16* [ %scevgep4, %vector.body ], [ %x, %vector.ph ]
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%lsr.iv1 = phi i16* [ %scevgep, %vector.body ], [ %y, %vector.ph ]
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%vec.phi = phi i32 [ 0, %vector.ph ], [ %16, %vector.body ]
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%7 = phi i32 [ %6, %vector.ph ], [ %17, %vector.body ]
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%8 = phi i32 [ %n, %vector.ph ], [ %10, %vector.body ]
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%lsr.iv12 = bitcast i16* %lsr.iv1 to <8 x i16>*
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%lsr.iv35 = bitcast i16* %lsr.iv3 to <8 x i16>*
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%9 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %8)
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%10 = sub i32 %8, 8
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%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv35, i32 2, <8 x i1> %9, <8 x i16> undef)
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%11 = sext <8 x i16> %wide.masked.load to <8 x i32>
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%wide.masked.load13 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv12, i32 2, <8 x i1> %9, <8 x i16> undef)
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%12 = sext <8 x i16> %wide.masked.load13 to <8 x i32>
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%13 = mul nsw <8 x i32> %12, %11
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%14 = select <8 x i1> %9, <8 x i32> %13, <8 x i32> zeroinitializer
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%15 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %14)
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%16 = add i32 %15, %vec.phi
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%scevgep = getelementptr i16, i16* %lsr.iv1, i32 8
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%scevgep4 = getelementptr i16, i16* %lsr.iv3, i32 8
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%17 = call i32 @llvm.loop.decrement.reg.i32(i32 %7, i32 1)
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%18 = icmp ne i32 %17, 0
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br i1 %18, label %vector.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %vector.body, %entry
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%s.0.lcssa = phi i32 [ 0, %entry ], [ %16, %vector.body ]
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ret i32 %s.0.lcssa
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}
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declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
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declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
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declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
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declare <8 x i1> @llvm.arm.mve.vctp16(i32)
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...
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---
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name: test
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: rgpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gprnopc, preferred-register: '' }
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- { id: 3, class: gprnopc, preferred-register: '' }
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- { id: 4, class: tgpreven, preferred-register: '' }
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- { id: 5, class: gprlr, preferred-register: '' }
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- { id: 6, class: rgpr, preferred-register: '' }
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- { id: 7, class: gpr, preferred-register: '' }
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- { id: 8, class: gpr, preferred-register: '' }
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- { id: 9, class: gpr, preferred-register: '' }
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- { id: 10, class: gpr, preferred-register: '' }
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- { id: 11, class: gpr, preferred-register: '' }
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- { id: 12, class: gpr, preferred-register: '' }
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- { id: 13, class: gpr, preferred-register: '' }
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- { id: 14, class: gpr, preferred-register: '' }
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- { id: 15, class: gprnopc, preferred-register: '' }
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- { id: 16, class: gpr, preferred-register: '' }
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- { id: 17, class: rgpr, preferred-register: '' }
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- { id: 18, class: rgpr, preferred-register: '' }
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- { id: 19, class: rgpr, preferred-register: '' }
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- { id: 20, class: rgpr, preferred-register: '' }
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- { id: 21, class: gprnopc, preferred-register: '' }
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- { id: 22, class: rgpr, preferred-register: '' }
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- { id: 23, class: gpr, preferred-register: '' }
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- { id: 24, class: gprlr, preferred-register: '' }
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- { id: 25, class: rgpr, preferred-register: '' }
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- { id: 26, class: vccr, preferred-register: '' }
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- { id: 27, class: rgpr, preferred-register: '' }
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- { id: 28, class: rgpr, preferred-register: '' }
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- { id: 29, class: mqpr, preferred-register: '' }
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- { id: 30, class: rgpr, preferred-register: '' }
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- { id: 31, class: mqpr, preferred-register: '' }
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- { id: 32, class: tgpreven, preferred-register: '' }
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- { id: 33, class: gprlr, preferred-register: '' }
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- { id: 34, class: gprlr, preferred-register: '' }
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- { id: 35, class: gprnopc, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%13' }
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- { reg: '$r1', virtual-reg: '%14' }
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- { reg: '$r2', virtual-reg: '%15' }
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body: |
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; CHECK-LABEL: name: test
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.2(0x50000000), %bb.1(0x30000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r2
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; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r0
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; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr
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; CHECK: bb.1:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[COPY3:%[0-9]+]]:gpr = COPY [[t2MOVi]]
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; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
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; CHECK: bb.2.vector.ph:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 7, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2BICri:%[0-9]+]]:rgpr = t2BICri [[t2ADDri]], 7, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2BICri]], 8, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2MOVi1:%[0-9]+]]:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2ADDrs:%[0-9]+]]:gprnopc = nuw nsw t2ADDrs [[t2MOVi1]], [[t2SUBri]], 27, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[COPY4:%[0-9]+]]:rgpr = COPY [[t2ADDrs]]
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; CHECK: [[t2DoLoopStart:%[0-9]+]]:gprlr = t2DoLoopStart [[COPY4]]
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; CHECK: [[t2MOVi2:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[COPY5:%[0-9]+]]:gpr = COPY [[t2MOVi2]]
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; CHECK: [[COPY6:%[0-9]+]]:gpr = COPY [[t2DoLoopStart]]
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; CHECK: [[COPY7:%[0-9]+]]:gprnopc = COPY [[COPY]]
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; CHECK: bb.3.vector.body:
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; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
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; CHECK: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY2]], %bb.2, %10, %bb.3
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; CHECK: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY1]], %bb.2, %9, %bb.3
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; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3
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; CHECK: [[PHI3:%[0-9]+]]:gprlr = PHI [[COPY6]], %bb.2, %11, %bb.3
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; CHECK: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY7]], %bb.2, %7, %bb.3
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; CHECK: [[MVE_VCTP16_:%[0-9]+]]:vccr = MVE_VCTP16 [[PHI4]], 0, $noreg
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; CHECK: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[PHI4]], 8, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[COPY8:%[0-9]+]]:gpr = COPY [[t2SUBri1]]
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; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI]], 16, 1, [[MVE_VCTP16_]] :: (load 16 from %ir.lsr.iv35, align 2)
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; CHECK: [[MVE_VLDRHU16_post2:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post3:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI1]], 16, 1, [[MVE_VCTP16_]] :: (load 16 from %ir.lsr.iv12, align 2)
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; CHECK: [[MVE_VMLADAVas16_:%[0-9]+]]:tgpreven = MVE_VMLADAVas16 [[PHI2]], killed [[MVE_VLDRHU16_post3]], killed [[MVE_VLDRHU16_post1]], 1, [[MVE_VCTP16_]]
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; CHECK: [[COPY9:%[0-9]+]]:gpr = COPY [[MVE_VMLADAVas16_]]
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; CHECK: [[COPY10:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post2]]
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; CHECK: [[COPY11:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post]]
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; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI3]], 1
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; CHECK: [[COPY12:%[0-9]+]]:gpr = COPY [[t2LoopDec]]
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; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def dead $cpsr
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; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
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; CHECK: bb.4.for.cond.cleanup:
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; CHECK: [[PHI5:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.1, [[COPY9]], %bb.3
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; CHECK: $r0 = COPY [[PHI5]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.4(0x30000000)
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liveins: $r0, $r1, $r2
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%15:gprnopc = COPY $r2
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%14:gpr = COPY $r1
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%13:gpr = COPY $r0
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t2CMPri %15, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.1, 10 /* CC::ge */, $cpsr
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bb.4:
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successors: %bb.3(0x80000000)
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%22:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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%16:gpr = COPY %22
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t2B %bb.3, 14 /* CC::al */, $noreg
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bb.1.vector.ph:
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successors: %bb.2(0x80000000)
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%17:rgpr = t2ADDri %15, 7, 14 /* CC::al */, $noreg, $noreg
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%18:rgpr = t2BICri %17, 7, 14 /* CC::al */, $noreg, $noreg
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%19:rgpr = t2SUBri %18, 8, 14 /* CC::al */, $noreg, $noreg
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%20:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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%21:gprnopc = nuw nsw t2ADDrs %20, %19, 27, 14 /* CC::al */, $noreg, $noreg
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%0:rgpr = COPY %21
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%24:gprlr = t2DoLoopStart %0
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%25:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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%23:gpr = COPY %25
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%1:gpr = COPY %24
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%35:gprnopc = COPY %15
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bb.2.vector.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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%2:gprnopc = PHI %13, %bb.1, %10, %bb.2
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%3:gprnopc = PHI %14, %bb.1, %9, %bb.2
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%4:tgpreven = PHI %23, %bb.1, %8, %bb.2
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%5:gprlr = PHI %1, %bb.1, %11, %bb.2
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%6:rgpr = PHI %35, %bb.1, %7, %bb.2
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%26:vccr = MVE_VCTP16 %6, 0, $noreg
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%27:rgpr = t2SUBri %6, 8, 14 /* CC::al */, $noreg, $noreg
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%7:gpr = COPY %27
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%28:rgpr, %29:mqpr = MVE_VLDRHU16_post %2, 16, 1, %26 :: (load 16 from %ir.lsr.iv35, align 2)
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%30:rgpr, %31:mqpr = MVE_VLDRHU16_post %3, 16, 1, %26 :: (load 16 from %ir.lsr.iv12, align 2)
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%32:tgpreven = MVE_VMLADAVas16 %4, killed %31, killed %29, 1, %26
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%8:gpr = COPY %32
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%9:gpr = COPY %30
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%10:gpr = COPY %28
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%33:gprlr = t2LoopDec %5, 1
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%11:gpr = COPY %33
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t2LoopEnd %33, %bb.2, implicit-def dead $cpsr
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t2B %bb.3, 14 /* CC::al */, $noreg
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bb.3.for.cond.cleanup:
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%12:gpr = PHI %16, %bb.4, %8, %bb.2
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$r0 = COPY %12
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tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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...
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