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Remove comparison methods for MVT. The main cause 

of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits.  Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.

llvm-svn: 52098
This commit is contained in:
Duncan Sands 2008-06-08 20:54:56 +00:00
parent b4866ef30c
commit 11dd424539
18 changed files with 129 additions and 117 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/include/llvm/CodeGen/SelectionDAG.h
View File

@ -610,7 +610,7 @@ private:
std::vector<CondCodeSDNode*> CondCodeNodes;
std::vector<SDNode*> ValueTypeNodes;
std::map<MVT, SDNode*> ExtendedValueTypeNodes;
std::map<MVT, SDNode*, MVT::compareRawBits> ExtendedValueTypeNodes;
std::map<std::string, SDNode*> ExternalSymbols;
std::map<std::string, SDNode*> TargetExternalSymbols;
std::map<std::string, StringSDNode*> StringNodes;

37
llvm/include/llvm/CodeGen/ValueTypes.h
View File

@ -132,16 +132,10 @@ namespace llvm {
MVT() {}
MVT(SimpleValueType S) { V = S; }
inline bool operator== (const MVT VT) const { return V == VT.V; }
inline bool operator!= (const MVT VT) const { return V != VT.V; }
/// FIXME: The following comparison methods are bogus - they are only here
/// to ease the transition to a struct type.
inline bool operator< (const MVT VT) const { return V < VT.V; }
inline bool operator<= (const MVT VT) const { return V <= VT.V; }
inline bool operator> (const MVT VT) const { return V > VT.V; }
inline bool operator>= (const MVT VT) const { return V >= VT.V; }
/// getIntegerVT - Returns the MVT that represents an integer with the given
/// number of bits.
static inline MVT getIntegerVT(unsigned BitWidth) {
@ -268,6 +262,27 @@ namespace llvm {
}
/// bitsGT - Return true if this has more bits than VT.
inline bool bitsGT(MVT VT) const {
return getSizeInBits() > VT.getSizeInBits();
}
/// bitsGE - Return true if this has no less bits than VT.
inline bool bitsGE(MVT VT) const {
return getSizeInBits() >= VT.getSizeInBits();
}
/// bitsLT - Return true if this has less bits than VT.
inline bool bitsLT(MVT VT) const {
return getSizeInBits() < VT.getSizeInBits();
}
/// bitsLE - Return true if this has no more bits than VT.
inline bool bitsLE(MVT VT) const {
return getSizeInBits() <= VT.getSizeInBits();
}
/// getSimpleVT - Return the SimpleValueType held in the specified
/// simple MVT.
inline SimpleValueType getSimpleVT() const {
@ -413,6 +428,14 @@ namespace llvm {
/// getRawBits - Represent the type as a bunch of bits.
uint32_t getRawBits() const { return V; }
/// compareRawBits - A meaningless but well-behaved order, useful for
/// constructing containers.
struct compareRawBits {
bool operator()(MVT L, MVT R) const {
return L.getRawBits() < R.getRawBits();
}
};
};
} // End llvm namespace

12
llvm/include/llvm/Target/TargetLowering.h
View File

@ -406,9 +406,9 @@ public:
"This operation isn't promoted!");
// See if this has an explicit type specified.
std::map<std::pair<unsigned, MVT>,
MVT>::const_iterator PTTI =
PromoteToType.find(std::make_pair(Op, VT));
std::map<std::pair<unsigned, MVT::SimpleValueType>,
MVT::SimpleValueType>::const_iterator PTTI =
PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
if (PTTI != PromoteToType.end()) return PTTI->second;
assert((VT.isInteger() || VT.isFloatingPoint()) &&
@ -898,7 +898,8 @@ protected:
/// one that works. If that default is insufficient, this method can be used
/// by the target to override the default.
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
DestVT.getSimpleVT();
}
/// addLegalFPImmediate - Indicate that this target can instruction select
@ -1427,7 +1428,8 @@ private:
///
/// Targets add entries to this map with AddPromotedToType(..), clients access
/// this with getTypeToPromoteTo(..).
std::map<std::pair<unsigned, MVT>, MVT> PromoteToType;
std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
PromoteToType;
/// LibcallRoutineNames - Stores the name each libcall.
///

44
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -1786,7 +1786,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
EVT = MVT::Other;
LoadedVT = LN0->getMemoryVT();
if (EVT != MVT::Other && LoadedVT > EVT &&
if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
MVT PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to
@ -2393,7 +2393,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
case 16: EVT = MVT::i16; break;
case 32: EVT = MVT::i32; break;
}
if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
if (EVT != MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
DAG.getValueType(EVT));
}
@ -2609,7 +2609,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
if (VT == VT0)
return XORNode;
AddToWorkList(XORNode.Val);
if (VT.getSizeInBits() > VT0.getSizeInBits())
if (VT.bitsGT(VT0))
return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
}
@ -2816,9 +2816,9 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// fold (sext (truncate x)) -> (sextinreg x).
if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
N0.getValueType())) {
if (Op.getValueType() < VT)
if (Op.getValueType().bitsLT(VT))
Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
else if (Op.getValueType() > VT)
else if (Op.getValueType().bitsGT(VT))
Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
DAG.getValueType(N0.getValueType()));
@ -2925,9 +2925,9 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
if (N0.getOpcode() == ISD::TRUNCATE &&
(!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
SDOperand Op = N0.getOperand(0);
if (Op.getValueType() < VT) {
if (Op.getValueType().bitsLT(VT)) {
Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
} else if (Op.getValueType() > VT) {
} else if (Op.getValueType().bitsGT(VT)) {
Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
}
return DAG.getZeroExtendInReg(Op, N0.getValueType());
@ -2938,9 +2938,9 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
SDOperand X = N0.getOperand(0).getOperand(0);
if (X.getValueType() < VT) {
if (X.getValueType().bitsLT(VT)) {
X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
} else if (X.getValueType() > VT) {
} else if (X.getValueType().bitsGT(VT)) {
X = DAG.getNode(ISD::TRUNCATE, VT, X);
}
APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
@ -3045,7 +3045,7 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
SDOperand TruncOp = N0.getOperand(0);
if (TruncOp.getValueType() == VT)
return TruncOp; // x iff x size == zext size.
if (TruncOp.getValueType() > VT)
if (TruncOp.getValueType().bitsGT(VT))
return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
}
@ -3055,9 +3055,9 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
SDOperand X = N0.getOperand(0).getOperand(0);
if (X.getValueType() < VT) {
if (X.getValueType().bitsLT(VT)) {
X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
} else if (X.getValueType() > VT) {
} else if (X.getValueType().bitsGT(VT)) {
X = DAG.getNode(ISD::TRUNCATE, VT, X);
}
APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
@ -3251,7 +3251,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
}
@ -3333,10 +3333,10 @@ SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
// fold (truncate (ext x)) -> (ext x) or (truncate x) or x
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
N0.getOpcode() == ISD::ANY_EXTEND) {
if (N0.getOperand(0).getValueType() < VT)
if (N0.getOperand(0).getValueType().bitsLT(VT))
// if the source is smaller than the dest, we still need an extend
return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
else if (N0.getOperand(0).getValueType() > VT)
else if (N0.getOperand(0).getValueType().bitsGT(VT))
// if the source is larger than the dest, than we just need the truncate
return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
else
@ -3946,7 +3946,7 @@ SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
SDOperand In = N0.getOperand(0);
if (In.getValueType() == VT) return In;
if (VT < In.getValueType())
if (VT.bitsLT(In.getValueType()))
return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
return DAG.getNode(ISD::FP_EXTEND, VT, In);
}
@ -4700,9 +4700,7 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
MVT LVT = EVT;
if (InVec.getOpcode() == ISD::BIT_CONVERT) {
MVT BCVT = InVec.getOperand(0).getValueType();
if (!BCVT.isVector()
|| (EVT.getSizeInBits() >
BCVT.getVectorElementType().getSizeInBits()))
if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
return SDOperand();
InVec = InVec.getOperand(0);
EVT = BCVT.getVectorElementType();
@ -5261,7 +5259,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
(N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
MVT XType = N0.getValueType();
MVT AType = N2.getValueType();
if (XType >= AType) {
if (XType.bitsGE(AType)) {
// and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
// single-bit constant.
if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
@ -5270,7 +5268,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
AddToWorkList(Shift.Val);
if (XType > AType) {
if (XType.bitsGT(AType)) {
Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
AddToWorkList(Shift.Val);
}
@ -5280,7 +5278,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
AddToWorkList(Shift.Val);
if (XType > AType) {
if (XType.bitsGT(AType)) {
Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
AddToWorkList(Shift.Val);
}
@ -5304,7 +5302,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
// cast from setcc result type to select result type
if (AfterLegalize) {
SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
if (N2.getValueType() < SCC.getValueType())
if (N2.getValueType().bitsLT(SCC.getValueType()))
Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
else
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);

20
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -789,7 +789,7 @@ PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
SPFI);
// Truncate or zero extend offset to target pointer type.
unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
// Add the offset to the index.
unsigned EltSize = EltVT.getSizeInBits()/8;
@ -4063,7 +4063,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
MVT NVT = TLI.getTypeToTransformTo(VT);
assert(getTypeAction(VT) == Promote &&
"Caller should expand or legalize operands that are not promotable!");
assert(NVT > VT && NVT.isInteger() == VT.isInteger() &&
assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
"Cannot promote to smaller type!");
SDOperand Tmp1, Tmp2, Tmp3;
@ -4110,9 +4110,9 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
switch (getTypeAction(Node->getOperand(0).getValueType())) {
case Legal:
Result = LegalizeOp(Node->getOperand(0));
assert(Result.getValueType() >= NVT &&
assert(Result.getValueType().bitsGE(NVT) &&
"This truncation doesn't make sense!");
if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
break;
case Promote:
@ -4574,7 +4574,7 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
DAG.getConstant(EltSize, Idx.getValueType()));
if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits())
if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
else
Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
@ -5352,7 +5352,7 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) {
if (DestTy == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0);
else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits())
else if (DestTy.bitsGT(MVT::f32))
// FIXME: Avoid the extend by construction the right constantpool?
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
CPIdx,
@ -5493,12 +5493,10 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
if (DestVT == MVT::f64) {
// do nothing
Result = Sub;
} else if (DestVT.getSizeInBits() <
MVT(MVT::f64).getSizeInBits()) {
} else if (DestVT.bitsLT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
DAG.getIntPtrConstant(0));
} else if (DestVT.getSizeInBits() >
MVT(MVT::f64).getSizeInBits()) {
} else if (DestVT.bitsGT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
}
return Result;
@ -5785,7 +5783,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
MVT NVT = TLI.getTypeToTransformTo(VT);
SDNode *Node = Op.Val;
assert(getTypeAction(VT) == Expand && "Not an expanded type!");
assert(((NVT.isInteger() && NVT < VT) || VT.isFloatingPoint() ||
assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
VT.isVector()) && "Cannot expand to FP value or to larger int value!");
// See if we already expanded it.

16
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
View File

@ -150,7 +150,7 @@ void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = N->getOperand(0);
if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) {
if (Op.getValueType().bitsLE(NVT)) {
// The low part is any extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
@ -171,7 +171,7 @@ void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = N->getOperand(0);
if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) {
if (Op.getValueType().bitsLE(NVT)) {
// The low part is zero extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
@ -195,7 +195,7 @@ void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = N->getOperand(0);
if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) {
if (Op.getValueType().bitsLE(NVT)) {
// The low part is sign extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
// The high part is obtained by SRA'ing all but one of the bits of low part.
@ -301,7 +301,7 @@ ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
GetExpandedOp(N->getOperand(0), Lo, Hi);
MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
if (EVT.getSizeInBits() <= Lo.getValueType().getSizeInBits()) {
if (EVT.bitsLE(Lo.getValueType())) {
// sext_inreg the low part if needed.
Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
N->getOperand(1));
@ -411,7 +411,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
// Handle endianness of the load.
if (TLI.isBigEndian())
std::swap(Lo, Hi);
} else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) {
} else if (N->getMemoryVT().bitsLE(NVT)) {
MVT EVT = N->getMemoryVT();
Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
@ -834,7 +834,7 @@ void DAGTypeLegalizer::ExpandResult_EXTRACT_VECTOR_ELT(SDNode *N,
SDOperand Idx = N->getOperand(1);
// Make sure the type of Idx is big enough to hold the new values.
if (Idx.getValueType().getSizeInBits() < TLI.getPointerTy().getSizeInBits())
if (Idx.getValueType().bitsLT(TLI.getPointerTy()))
Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx);
@ -1179,7 +1179,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
SDOperand FudgeInReg;
if (DestTy == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits())
else if (DestTy.bitsGT(MVT::f32))
// FIXME: Avoid the extend by construction the right constantpool?
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
CPIdx, NULL, 0, MVT::f32);
@ -1371,7 +1371,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVolatile, MinAlign(Alignment, IncrementSize));
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
} else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) {
} else if (N->getMemoryVT().bitsLE(NVT)) {
GetExpandedOp(N->getValue(), Lo, Hi);
return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
N->getMemoryVT(), isVolatile, Alignment);

6
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp
View File

@ -252,12 +252,10 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) {
if (DestVT == MVT::f64) {
// do nothing
Result = Sub;
} else if (DestVT.getSizeInBits() <
MVT(MVT::f64).getSizeInBits()) {
} else if (DestVT.bitsLT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
DAG.getIntPtrConstant(0));
} else if (DestVT.getSizeInBits() >
MVT(MVT::f64).getSizeInBits()) {
} else if (DestVT.bitsGT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
}
return BitConvertToInteger(Result);

2
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp
View File

@ -126,7 +126,7 @@ SDOperand DAGTypeLegalizer::ScalarizeRes_INSERT_VECTOR_ELT(SDNode *N) {
// so be sure to truncate it to the element type if necessary.
SDOperand Op = N->getOperand(1);
MVT EltVT = N->getValueType(0).getVectorElementType();
if (Op.getValueType().getSizeInBits() > EltVT.getSizeInBits())
if (Op.getValueType().bitsGT(EltVT))
Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
assert(Op.getValueType() == EltVT && "Invalid type for inserted value!");
return Op;

2
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp
View File

@ -483,7 +483,7 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) {
Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
DAG.getConstant(EltSize, Idx.getValueType()));
if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits())
if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
else
Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);

36
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1983,7 +1983,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) {
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
"Invalid SIGN_EXTEND!");
if (Operand.getValueType() == VT) return Operand; // noop extension
assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits()
assert(Operand.getValueType().bitsLT(VT)
&& "Invalid sext node, dst < src!");
if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
@ -1992,7 +1992,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) {
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
"Invalid ZERO_EXTEND!");
if (Operand.getValueType() == VT) return Operand; // noop extension
assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits()
assert(Operand.getValueType().bitsLT(VT)
&& "Invalid zext node, dst < src!");
if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0));
@ -2001,7 +2001,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) {
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
"Invalid ANY_EXTEND!");
if (Operand.getValueType() == VT) return Operand; // noop extension
assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits()
assert(Operand.getValueType().bitsLT(VT)
&& "Invalid anyext node, dst < src!");
if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
@ -2011,18 +2011,16 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) {
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
"Invalid TRUNCATE!");
if (Operand.getValueType() == VT) return Operand; // noop truncate
assert(Operand.getValueType().getSizeInBits() > VT.getSizeInBits()
assert(Operand.getValueType().bitsGT(VT)
&& "Invalid truncate node, src < dst!");
if (OpOpcode == ISD::TRUNCATE)
return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0));
else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
OpOpcode == ISD::ANY_EXTEND) {
// If the source is smaller than the dest, we still need an extend.
if (Operand.Val->getOperand(0).getValueType().getSizeInBits()
< VT.getSizeInBits())
if (Operand.Val->getOperand(0).getValueType().bitsLT(VT))
return getNode(OpOpcode, VT, Operand.Val->getOperand(0));
else if (Operand.Val->getOperand(0).getValueType().getSizeInBits()
> VT.getSizeInBits())
else if (Operand.Val->getOperand(0).getValueType().bitsGT(VT))
return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0));
else
return Operand.Val->getOperand(0);
@ -2156,15 +2154,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
assert(VT == N1.getValueType() && "Not an inreg round!");
assert(VT.isFloatingPoint() && EVT.isFloatingPoint() &&
"Cannot FP_ROUND_INREG integer types");
assert(EVT.getSizeInBits() <= VT.getSizeInBits() &&
"Not rounding down!");
assert(EVT.bitsLE(VT) && "Not rounding down!");
if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
break;
}
case ISD::FP_ROUND:
assert(VT.isFloatingPoint() &&
N1.getValueType().isFloatingPoint() &&
VT.getSizeInBits() <= N1.getValueType().getSizeInBits() &&
VT.bitsLE(N1.getValueType()) &&
isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
if (N1.getValueType() == VT) return N1; // noop conversion.
break;
@ -2174,8 +2171,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
assert(VT == N1.getValueType() && "Not an inreg extend!");
assert(VT.isInteger() && EVT.isInteger() &&
"Cannot *_EXTEND_INREG FP types");
assert(EVT.getSizeInBits() <= VT.getSizeInBits() &&
"Not extending!");
assert(EVT.bitsLE(VT) && "Not extending!");
if (VT == EVT) return N1; // noop assertion.
break;
}
@ -2184,8 +2180,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
assert(VT == N1.getValueType() && "Not an inreg extend!");
assert(VT.isInteger() && EVT.isInteger() &&
"Cannot *_EXTEND_INREG FP types");
assert(EVT.getSizeInBits() <= VT.getSizeInBits() &&
"Not extending!");
assert(EVT.bitsLE(VT) && "Not extending!");
if (EVT == VT) return N1; // Not actually extending
if (N1C) {
@ -2652,7 +2647,7 @@ bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1);
assert(LVT.isInteger());
if (VT > LVT)
if (VT.bitsGT(LVT))
VT = LVT;
}
@ -2959,7 +2954,7 @@ SDOperand SelectionDAG::getMemset(SDOperand Chain, SDOperand Dst,
Entry.Node = Dst; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend or truncate the argument to be an i32 value for the call.
if (Src.getValueType() > MVT::i32)
if (Src.getValueType().bitsGT(MVT::i32))
Src = getNode(ISD::TRUNCATE, MVT::i32, Src);
else
Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src);
@ -3045,7 +3040,7 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
if (VT.isVector())
assert(EVT == VT.getVectorElementType() && "Invalid vector extload!");
else
assert(EVT.getSizeInBits() < VT.getSizeInBits() &&
assert(EVT.bitsLT(VT) &&
"Should only be an extending load, not truncating!");
assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
"Cannot sign/zero extend a FP/Vector load!");
@ -3154,8 +3149,7 @@ SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Val,
if (VT == SVT)
return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
assert(VT.getSizeInBits() > SVT.getSizeInBits() &&
"Not a truncation?");
assert(VT.bitsGT(SVT) && "Not a truncation?");
assert(VT.isInteger() == SVT.isInteger() &&
"Can't do FP-INT conversion!");
@ -4228,7 +4222,7 @@ void SDNode::Profile(FoldingSetNodeID &ID) {
///
const MVT *SDNode::getValueTypeList(MVT VT) {
if (VT.isExtended()) {
static std::set<MVT> EVTs;
static std::set<MVT, MVT::compareRawBits> EVTs;
return &(*EVTs.insert(VT).first);
} else {
static MVT VTs[MVT::LAST_VALUETYPE];

36
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -918,7 +918,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
if (PartVT.isInteger() &&
ValueVT.isInteger()) {
if (ValueVT.getSizeInBits() < PartVT.getSizeInBits()) {
if (ValueVT.bitsLT(PartVT)) {
// For a truncate, see if we have any information to
// indicate whether the truncated bits will always be
// zero or sign-extension.
@ -932,7 +932,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
}
if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
if (ValueVT < Val.getValueType())
if (ValueVT.bitsLT(Val.getValueType()))
// FP_ROUND's are always exact here.
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
DAG.getIntPtrConstant(1));
@ -1268,7 +1268,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
// at least 32-bit. But this is not necessary for non-C calling conventions.
if (VT.isInteger()) {
MVT MinVT = TLI.getRegisterType(MVT::i32);
if (VT.getSizeInBits() < MinVT.getSizeInBits())
if (VT.bitsLT(MinVT))
VT = MinVT;
}
@ -1655,7 +1655,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
// register so it can be used as an index into the jump table in a
// subsequent basic block. This value may be smaller or larger than the
// target's pointer type, and therefore require extension or truncating.
if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits())
if (VT.bitsGT(TLI.getPointerTy()))
SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
else
SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
@ -1705,7 +1705,7 @@ void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B)
ISD::SETUGT);
SDOperand ShiftOp;
if (VT.getSizeInBits() > TLI.getShiftAmountTy().getSizeInBits())
if (VT.bitsGT(TLI.getShiftAmountTy()))
ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
else
ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
@ -2386,10 +2386,9 @@ void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
if (TLI.getShiftAmountTy().getSizeInBits() <
Op2.getValueType().getSizeInBits())
if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
else if (TLI.getShiftAmountTy() > Op2.getValueType())
else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
@ -2611,7 +2610,7 @@ void SelectionDAGLowering::visitPtrToInt(User &I) {
MVT SrcVT = N.getValueType();
MVT DestVT = TLI.getValueType(I.getType());
SDOperand Result;
if (DestVT.getSizeInBits() < SrcVT.getSizeInBits())
if (DestVT.bitsLT(SrcVT))
Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
else
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
@ -2625,7 +2624,7 @@ void SelectionDAGLowering::visitIntToPtr(User &I) {
SDOperand N = getValue(I.getOperand(0));
MVT SrcVT = N.getValueType();
MVT DestVT = TLI.getValueType(I.getType());
if (DestVT.getSizeInBits() < SrcVT.getSizeInBits())
if (DestVT.bitsLT(SrcVT))
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
else
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
@ -2777,9 +2776,9 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
// If the index is smaller or larger than intptr_t, truncate or extend
// it.
if (IdxN.getValueType() < N.getValueType()) {
if (IdxN.getValueType().bitsLT(N.getValueType())) {
IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
} else if (IdxN.getValueType() > N.getValueType())
} else if (IdxN.getValueType().bitsGT(N.getValueType()))
IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
// If this is a multiply by a power of two, turn it into a shl
@ -2814,9 +2813,9 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
SDOperand AllocSize = getValue(I.getArraySize());
MVT IntPtr = TLI.getPointerTy();
if (IntPtr < AllocSize.getValueType())
if (IntPtr.bitsLT(AllocSize.getValueType()))
AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
else if (IntPtr > AllocSize.getValueType())
else if (IntPtr.bitsGT(AllocSize.getValueType()))
AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
@ -3325,7 +3324,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
case Intrinsic::eh_dwarf_cfa: {
MVT VT = getValue(I.getOperand(1)).getValueType();
SDOperand CfaArg;
if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits())
if (VT.bitsGT(TLI.getPointerTy()))
CfaArg = DAG.getNode(ISD::TRUNCATE,
TLI.getPointerTy(), getValue(I.getOperand(1)));
else
@ -3827,8 +3826,7 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF,
// If we have already found this register in a different register class,
// choose the one with the largest VT specified. For example, on
// PowerPC, we favor f64 register classes over f32.
if (FoundVT == MVT::Other ||
FoundVT.getSizeInBits() < (*I).getSizeInBits()) {
if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
ThisVT = *I;
break;
}
@ -4478,9 +4476,9 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) {
MVT IntPtr = TLI.getPointerTy();
if (IntPtr < Src.getValueType())
if (IntPtr.bitsLT(Src.getValueType()))
Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
else if (IntPtr > Src.getValueType())
else if (IntPtr.bitsGT(Src.getValueType()))
Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
// Scale the source by the type size.

2
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -384,7 +384,7 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT VT,
MVT DestVT = getTypeToTransformTo(NewVT);
RegisterVT = DestVT;
if (DestVT < NewVT) {
if (DestVT.bitsLT(NewVT)) {
// Value is expanded, e.g. i64 -> i16.
return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
} else {

2
llvm/lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -356,7 +356,7 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
std::vector<MVT> RetVals;
MVT RetTyVT = getValueType(RetTy);
MVT ActualRetTyVT = RetTyVT;
if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
ActualRetTyVT = MVT::i64;
if (RetTyVT != MVT::isVoid)

2
llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -112,7 +112,7 @@ namespace {
{
MVT vt = CN->getValueType(0);
Imm = (short) CN->getValue();
if (vt >= MVT::i1 && vt <= MVT::i16) {
if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
return true;
} else if (vt == MVT::i32) {
int32_t i_val = (int32_t) CN->getValue();

8
llvm/lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -2218,7 +2218,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
N1Opc = (N1.getValueType() < MVT::i16 ? ISD::ZERO_EXTEND : ISD::TRUNCATE);
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::ZERO_EXTEND : ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
@ -2236,7 +2236,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
N1Opc = (N1.getValueType() < MVT::i16 ? ISD::ZERO_EXTEND : ISD::TRUNCATE);
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::ZERO_EXTEND : ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
@ -2249,7 +2249,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
N1Opc = (N1.getValueType() < MVT::i16 ? ISD::SIGN_EXTEND : ISD::TRUNCATE);
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::SIGN_EXTEND : ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
@ -2262,7 +2262,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
N1Opc = (N1.getValueType() < MVT::i16 ? ISD::SIGN_EXTEND : ISD::TRUNCATE);
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::SIGN_EXTEND : ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));

2
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1173,7 +1173,7 @@ SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
if (C->isNullValue() && CC == ISD::SETEQ) {
MVT VT = Op.getOperand(0).getValueType();
SDOperand Zext = Op.getOperand(0);
if (VT < MVT::i32) {
if (VT.bitsLT(MVT::i32)) {
VT = MVT::i32;
Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
}

13
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -4410,7 +4410,7 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
MVT SrcVT = Op.getOperand(0).getValueType();
assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
"Unknown SINT_TO_FP to lower!");
// These are really Legal; caller falls through into that case.
@ -4470,7 +4470,8 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
std::pair<SDOperand,SDOperand> X86TargetLowering::
FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
Op.getValueType().getSimpleVT() >= MVT::i16 &&
"Unknown FP_TO_SINT to lower!");
// These are really Legal.
@ -4607,12 +4608,12 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
MVT SrcVT = Op1.getValueType();
// If second operand is smaller, extend it first.
if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
if (SrcVT.bitsLT(VT)) {
Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
SrcVT = VT;
}
// And if it is bigger, shrink it first.
if (SrcVT.getSizeInBits() > VT.getSizeInBits()) {
if (SrcVT.bitsGT(VT)) {
Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
SrcVT = VT;
}
@ -4639,7 +4640,7 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
// Shift sign bit right or left if the two operands have different types.
if (SrcVT.getSizeInBits() > VT.getSizeInBits()) {
if (SrcVT.bitsGT(VT)) {
// Op0 is MVT::f32, Op1 is MVT::f64.
SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
@ -4909,7 +4910,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
break;
}
if (AVT > MVT::i8) {
if (AVT.bitsGT(MVT::i8)) {
unsigned UBytes = AVT.getSizeInBits() / 8;
Count = DAG.getIntPtrConstant(SizeVal / UBytes);
BytesLeft = SizeVal % UBytes;

4
llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp
View File

@ -339,10 +339,10 @@ static bool OptimizeNoopCopyExpression(CastInst *CI, const TargetLowering &TLI){
// This is an fp<->int conversion?
if (SrcVT.isInteger() != DstVT.isInteger())
return false;
// If this is an extension, it will be a zero or sign extension, which
// isn't a noop.
if (SrcVT < DstVT) return false;
if (SrcVT.bitsLT(DstVT)) return false;
// If these values will be promoted, find out what they will be promoted
// to. This helps us consider truncates on PPC as noop copies when they