From 11a5ae0880f5088aaf0231545fbdd3953a1dada1 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Thu, 2 Oct 2014 07:17:15 +0000 Subject: [PATCH] [x86] Minimize the parameters to this test for clarity. The test has to do with DAG combines, and so it doesn't need the new vector shuffle lowering to be effective. Also, it has a nice in-IR triple string which we should really be using rather than command line flags (unless it varies form RUN-line to RUN-line). Finally, I much prefer letting LLVM synthesize the correct datalayout string from the triple rather than baking one in here that will just become stale. llvm-svn: 218856 --- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll index 5a52403394ae..8cb33af47fff 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll @@ -1,11 +1,10 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-SSE2 +; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=CHECK-SSE2 ; ; Verify that the DAG combiner correctly folds bitwise operations across ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other ; basic and always-safe patterns. Also test that the DAG combiner will combine ; target-specific shuffle instructions where reasonable. -target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-unknown" declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)