forked from OSchip/llvm-project
[AMDGPU] Support mov dpp with 64 bit operands
We define mov/update dpp intrinsics as overloaded but do not support i64, which is a practically useful type. Fix the selection and lowering. Differential Revision: https://reviews.llvm.org/D68673 llvm-svn: 374910
This commit is contained in:
Stanislav Mekhanoshin
parent
034badb312
commit
1184c27fa5
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@ -557,6 +557,13 @@ bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
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if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) {
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Changed = true;
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++NumDPPMovsCombined;
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} else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO) {
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auto Split = TII->expandMovDPP64(MI);
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for (auto M : { Split.first, Split.second }) {
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if (combineDPPMov(*M))
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++NumDPPMovsCombined;
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}
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Changed = true;
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}
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}
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}
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@ -1454,6 +1454,10 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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MI.eraseFromParent();
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break;
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}
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case AMDGPU::V_MOV_B64_DPP_PSEUDO: {
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expandMovDPP64(MI);
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break;
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}
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case AMDGPU::V_SET_INACTIVE_B32: {
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unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
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unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
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@ -1567,6 +1571,64 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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return true;
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}
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std::pair<MachineInstr*, MachineInstr*>
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SIInstrInfo::expandMovDPP64(MachineInstr &MI) const {
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assert (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MBB.findDebugLoc(MI);
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MachineFunction *MF = MBB.getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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Register Dst = MI.getOperand(0).getReg();
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unsigned Part = 0;
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MachineInstr *Split[2];
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for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) {
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auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
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if (Dst.isPhysical()) {
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MovDPP.addDef(RI.getSubReg(Dst, Sub));
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} else {
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assert(MRI.isSSA());
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auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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MovDPP.addDef(Tmp);
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}
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for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
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const MachineOperand &SrcOp = MI.getOperand(I);
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assert(!SrcOp.isFPImm());
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if (SrcOp.isImm()) {
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APInt Imm(64, SrcOp.getImm());
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Imm.ashrInPlace(Part * 32);
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MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
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} else {
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assert(SrcOp.isReg());
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Register Src = SrcOp.getReg();
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if (Src.isPhysical())
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MovDPP.addReg(RI.getSubReg(Src, Sub));
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else
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MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
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}
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}
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for (unsigned I = 3; I < MI.getNumExplicitOperands(); ++I)
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MovDPP.addImm(MI.getOperand(I).getImm());
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Split[Part] = MovDPP;
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++Part;
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}
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if (Dst.isVirtual())
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BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
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.addReg(Split[0]->getOperand(0).getReg())
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.addImm(AMDGPU::sub0)
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.addReg(Split[1]->getOperand(0).getReg())
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.addImm(AMDGPU::sub1);
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MI.eraseFromParent();
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return std::make_pair(Split[0], Split[1]);
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}
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bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,
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MachineOperand &Src0,
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unsigned Src0OpName,
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@ -229,6 +229,14 @@ public:
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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// Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
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// instructions. Returns a pair of generated instructions.
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// Can split either post-RA with physical registers or pre-RA with
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// virtual registers. In latter case IR needs to be in SSA form and
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// and a REG_SEQUENCE is produced to define original register.
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std::pair<MachineInstr*, MachineInstr*>
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expandMovDPP64(MachineInstr &MI) const;
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// Returns an opcode that can be used to move a value to a \p DstRC
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// register. If there is no hardware instruction that can store to \p
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// DstRC, then AMDGPU::COPY is returned.
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@ -92,6 +92,11 @@ def ATOMIC_FENCE : SPseudoInstSI<
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let maybeAtomic = 1;
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}
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def VOP_I64_I64_DPP : VOPProfile <[i64, i64, untyped, untyped]> {
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let HasExt = 1;
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let HasExtDPP = 1;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
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// For use in patterns
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@ -107,6 +112,11 @@ def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
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def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
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(ins VSrc_b64:$src0)>;
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// 64-bit vector move with dpp. Expanded post-RA.
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def V_MOV_B64_DPP_PSEUDO : VOP_DPP_Pseudo <"v_mov_b64_dpp", VOP_I64_I64_DPP> {
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let Size = 16; // Requires two 8-byte v_mov_b32_dpp to complete.
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}
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// Pseudoinstruction for @llvm.amdgcn.wqm. It is turned into a copy after the
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// WQM pass processes it.
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def WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
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@ -1855,6 +1865,22 @@ def : GCNPat <
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(INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
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>;
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def : GCNPat <
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(i64 (int_amdgcn_mov_dpp i64:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
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timm:$bound_ctrl)),
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(V_MOV_B64_DPP_PSEUDO $src, $src, (as_i32imm $dpp_ctrl),
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(as_i32imm $row_mask), (as_i32imm $bank_mask),
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(as_i1imm $bound_ctrl))
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>;
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def : GCNPat <
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(i64 (int_amdgcn_update_dpp i64:$old, i64:$src, timm:$dpp_ctrl, timm:$row_mask,
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timm:$bank_mask, timm:$bound_ctrl)),
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(V_MOV_B64_DPP_PSEUDO $old, $src, (as_i32imm $dpp_ctrl),
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(as_i32imm $row_mask), (as_i32imm $bank_mask),
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(as_i1imm $bound_ctrl))
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>;
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//===----------------------------------------------------------------------===//
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// Fract Patterns
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//===----------------------------------------------------------------------===//
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@ -718,3 +718,43 @@ body: |
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%6:vgpr_32 = V_ADD_I32_e32 %5.sub0, %8, implicit-def $vcc, implicit $exec
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%7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %8, implicit-def $vcc, implicit $vcc, implicit $exec
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...
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# GCN-LABEL: name: dpp64_add64_impdef
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# GCN: %3:vgpr_32 = V_ADD_I32_dpp %1.sub0, %0.sub0, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
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# GCN: %5:vgpr_32 = V_ADDC_U32_dpp %1.sub1, %0.sub1, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
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name: dpp64_add64_impdef
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:vreg_64 = IMPLICIT_DEF
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%1:vreg_64 = IMPLICIT_DEF
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%2:vreg_64 = V_MOV_B64_DPP_PSEUDO %1:vreg_64, %0:vreg_64, 1, 15, 15, 1, implicit $exec
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%5:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %4:vgpr_32, implicit-def $vcc, implicit $exec
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%6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec
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...
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# GCN-LABEL: name: dpp64_add64_undef
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# GCN: %3:vgpr_32 = V_ADD_I32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
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# GCN: %5:vgpr_32 = V_ADDC_U32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
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name: dpp64_add64_undef
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tracksRegLiveness: true
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body: |
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bb.0:
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%2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
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%5:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %4:vgpr_32, implicit-def $vcc, implicit $exec
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%6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec
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...
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# GCN-LABEL: name: dpp64_add64_first_combined
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# GCN: %8:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, 1, 15, 15, 1, implicit $exec
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# GCN: %0:vreg_64 = REG_SEQUENCE undef %7:vgpr_32, %subreg.sub0, %8, %subreg.sub1
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# GCN: %3:vgpr_32 = V_ADD_I32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
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# GCN: %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %0.sub1, undef $vcc, 0, implicit $exec
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name: dpp64_add64_first_combined
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tracksRegLiveness: true
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body: |
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bb.0:
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%2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
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%4:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %3:vgpr_32, implicit-def $vcc, implicit $exec
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%5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %2.sub1, undef $vcc, 0, implicit $exec
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...
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@ -77,7 +77,31 @@ endif:
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ret void
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}
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; VI-LABEL: {{^}}mov_dpp64_test:
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; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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define amdgpu_kernel void @mov_dpp64_test(i64 addrspace(1)* %out, i64 %in1) {
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%tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 %in1, i32 1, i32 1, i32 1, i1 0) #0
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store i64 %tmp0, i64 addrspace(1)* %out
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ret void
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}
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; VI-LABEL: {{^}}mov_dpp64_imm_test:
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; VI-OPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9
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; VI-OPT-DAG: s_movk_i32 s[[SOLD_HI:[0-9]+]], 0x7047
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; VI-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], s[[SOLD_LO]]
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; VI-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], s[[SOLD_HI]]
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; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; VI-NOOPT-COUNT2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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define amdgpu_kernel void @mov_dpp64_imm_test(i64 addrspace(1)* %out) {
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%tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 123451234512345, i32 1, i32 1, i32 1, i1 0) #0
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store i64 %tmp0, i64 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.mov.dpp.i64(i64, i32, i32, i32, i1) #0
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attributes #0 = { nounwind readnone convergent }
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@ -1,10 +1,13 @@
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10 %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-OPT,GCN-OPT %s
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; RUN: llc -march=amdgcn -mcpu=tonga -O0 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-NOOPT %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GCN-OPT %s
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; GCN-LABEL: {{^}}dpp_test:
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; GCN: v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}}
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; GCN: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
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; GFX8: s_nop 1
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; GFX8-OPT: s_nop 1
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; GFX8-NOOPT: s_nop 0
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; GFX8-NOOPT-NEXT: s_nop 0
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; GCN: v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
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define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
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%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 0) #0
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@ -15,7 +18,9 @@ define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2)
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; GCN-LABEL: {{^}}dpp_test_bc:
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; GCN: v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}}
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; GCN: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
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; GFX8: s_nop 1
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; GFX8-OPT: s_nop 1
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; GFX8-NOOPT: s_nop 0
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; GFX8-NOOPT-NEXT: s_nop 0
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; GCN: v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[2,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0{{$}}
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define amdgpu_kernel void @dpp_test_bc(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
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%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 2, i32 1, i32 1, i1 1) #0
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@ -24,14 +29,14 @@ define amdgpu_kernel void @dpp_test_bc(i32 addrspace(1)* %out, i32 %in1, i32 %in
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}
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; VI-LABEL: {{^}}dpp_test1:
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; GCN-LABEL: {{^}}dpp_test1:
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; GFX10: v_add_nc_u32_e32 [[REG:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GFX8-OPT: v_add_u32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX8-NOOPT: v_add_u32_e64 [[REG:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX8-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GFX8: s_nop 0
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; GFX8-NEXT: s_nop 0
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; GFX8-OPT-NEXT: v_mov_b32_dpp {{v[0-9]+}}, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
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; GFX8-NEXT: v_mov_b32_dpp {{v[0-9]+}}, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
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@0 = internal unnamed_addr addrspace(3) global [448 x i32] undef, align 4
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define weak_odr amdgpu_kernel void @dpp_test1(i32* %arg) local_unnamed_addr {
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bb:
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@ -50,8 +55,56 @@ bb:
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ret void
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}
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; GCN-LABEL: {{^}}update_dpp64_test:
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; GCN: load_dwordx2 v{{\[}}[[SRC_LO:[0-9]+]]:[[SRC_HI:[0-9]+]]]
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; GCN-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
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; GCN-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
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define amdgpu_kernel void @update_dpp64_test(i64 addrspace(1)* %arg, i64 %in1, i64 %in2) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
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%load = load i64, i64 addrspace(1)* %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 1, i32 1, i1 0) #0
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store i64 %tmp0, i64 addrspace(1)* %gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}update_dpp64_imm_old_test:
|
||||
; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], 0x3afaedd9
|
||||
; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], 0x7047
|
||||
; GFX8-NOOPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9
|
||||
; GFX8-NOOPT-DAG: s_movk_i32 s[[SOLD_HI:[0-9]+]], 0x7047
|
||||
; GCN-DAG: load_dwordx2 v{{\[}}[[SRC_LO:[0-9]+]]:[[SRC_HI:[0-9]+]]]
|
||||
; GCN-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
|
||||
; GCN-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
|
||||
; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
|
||||
; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
|
||||
define amdgpu_kernel void @update_dpp64_imm_old_test(i64 addrspace(1)* %arg, i64 %in2) {
|
||||
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
|
||||
%load = load i64, i64 addrspace(1)* %gep
|
||||
%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 123451234512345, i64 %load, i32 1, i32 1, i32 1, i1 0) #0
|
||||
store i64 %tmp0, i64 addrspace(1)* %gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}update_dpp64_imm_src_test:
|
||||
; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], 0x3afaedd9
|
||||
; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], 0x7047
|
||||
; GFX8-NOOPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9
|
||||
; GFX8-NOOPT-DAG: s_movk_i32 s[[SOLD_HI:[0-9]+]], 0x7047
|
||||
; GCN-OPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
|
||||
; GCN-OPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
|
||||
; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
|
||||
; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
|
||||
define amdgpu_kernel void @update_dpp64_imm_src_test(i64 addrspace(1)* %out, i64 %in1) {
|
||||
%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 123451234512345, i32 1, i32 1, i32 1, i1 0) #0
|
||||
store i64 %tmp0, i64 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x()
|
||||
declare void @llvm.amdgcn.s.barrier()
|
||||
declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
|
||||
declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32, i32, i32, i1) #0
|
||||
|
||||
attributes #0 = { nounwind readnone convergent }
|
||||
|
|
|
|||
Loading…
Reference in New Issue