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These are done / no longer care. 

llvm-svn: 85798
This commit is contained in:
Evan Cheng 2009-11-02 07:58:25 +00:00
parent f6f1b37f9f
commit 115cfc07d5
1 changed files with 0 additions and 21 deletions
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21
llvm/lib/Target/ARM/README.txt
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@ -8,12 +8,8 @@ Reimplement 'select' in terms of 'SEL'.
add doesn't need to overflow between the two 16-bit chunks. add doesn't need to overflow between the two 16-bit chunks.
* Implement pre/post increment support. (e.g. PR935) * Implement pre/post increment support. (e.g. PR935)
* Coalesce stack slots!
* Implement smarter constant generation for binops with large immediates. * Implement smarter constant generation for binops with large immediates.
* Consider materializing FP constants like 0.0f and 1.0f using integer
immediate instructions then copy to FPU. Slower than load into FPU?
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the
@ -422,14 +418,6 @@ are not remembered when the same two values are compared twice.
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
More register scavenging work:
1. Use the register scavenger to track frame index materialized into registers
(those that do not fit in addressing modes) to allow reuse in the same BB.
2. Finish scavenging for Thumb.
//===---------------------------------------------------------------------===//
More LSR enhancements possible: More LSR enhancements possible:
1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged 1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
@ -540,10 +528,6 @@ while ARMConstantIslandPass only need to worry about LDR (literal).
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
We need to fix constant isel for ARMv6t2 to use MOVT.
//===---------------------------------------------------------------------===//
Constant island pass should make use of full range SoImm values for LEApcrel. Constant island pass should make use of full range SoImm values for LEApcrel.
Be careful though as the last attempt caused infinite looping on lencod. Be careful though as the last attempt caused infinite looping on lencod.
@ -593,11 +577,6 @@ it saves an instruction and a register.
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
add/sub/and/or + i32 imm can be simplified by folding part of the immediate
into the operation.
//===---------------------------------------------------------------------===//
It might be profitable to cse MOVi16 if there are lots of 32-bit immediates It might be profitable to cse MOVi16 if there are lots of 32-bit immediates
with the same bottom half. with the same bottom half.