forked from OSchip/llvm-project
parent
57431c9680
commit
11587d97be
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@ -904,12 +904,10 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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}
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case AMDGPU::SI_PC_ADD_REL_OFFSET: {
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const SIRegisterInfo *TRI
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= static_cast<const SIRegisterInfo *>(ST.getRegisterInfo());
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MachineFunction &MF = *MBB.getParent();
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unsigned Reg = MI.getOperand(0).getReg();
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unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0);
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unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1);
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unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
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unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
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// Create a bundle so these instructions won't be re-ordered by the
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// post-RA scheduler.
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