forked from OSchip/llvm-project
MachineFrameInfo: Simplify pristine register calculation.
About pristine regsiters: Pristine registers "hold a value that is useless to the current function, but that must be preserved - they are callee saved registers that have not been saved." This concept saves compile time as it frees the prologue/epilogue inserter from adding every such register to every basic blocks live-in list. However the current code in getPristineRegs is formulated in a complicated way: Inside the function prologue and epilogue all callee saves are considered pristine, while in the rest of the code only the non-saved ones are considered pristine. This requires logic to differentiate between prologue/epilogue and the rest and in the presence of shrink-wrapping this even becomes complicated/expensive. It's also unnecessary because the prologue epilogue inserters already mark callee-save registers that are saved/restores properly in the respective blocks in the prologue/epilogue (see updateLiveness() in PrologueEpilogueInserter.cpp). So only declaring non-saved/restored callee saved registers as pristine just works. Differential Revision: http://reviews.llvm.org/D10101 llvm-svn: 238524
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@ -256,11 +256,6 @@ class MachineFrameInfo {
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/// Not null, if shrink-wrapping found a better place for the epilogue.
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MachineBasicBlock *Restore;
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/// Check if it exists a path from \p MBB leading to the basic
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/// block with a SavePoint (a.k.a. prologue).
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bool isBeforeSavePoint(const MachineFunction &MF,
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const MachineBasicBlock &MBB) const;
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public:
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explicit MachineFrameInfo(unsigned StackAlign, bool isStackRealign,
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bool RealignOpt)
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@ -627,16 +622,15 @@ public:
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MachineBasicBlock *getRestorePoint() const { return Restore; }
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void setRestorePoint(MachineBasicBlock *NewRestore) { Restore = NewRestore; }
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/// getPristineRegs - Return a set of physical registers that are pristine on
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/// entry to the MBB.
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/// Return a set of physical registers that are pristine.
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///
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/// Pristine registers hold a value that is useless to the current function,
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/// but that must be preserved - they are callee saved registers that have not
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/// been saved yet.
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/// but that must be preserved - they are callee saved registers that are not
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/// saved.
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///
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/// Before the PrologueEpilogueInserter has placed the CSR spill code, this
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/// method always returns an empty set.
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BitVector getPristineRegs(const MachineBasicBlock *MBB) const;
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BitVector getPristineRegs(const MachineFunction &MF) const;
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/// print - Used by the MachineFunction printer to print information about
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/// stack objects. Implemented in MachineFunction.cpp
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@ -163,7 +163,7 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
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// all callee-saved registers. In non-return this is any
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// callee-saved register that is not saved in the prolog.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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BitVector Pristine = MFI->getPristineRegs(BB);
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BitVector Pristine = MFI->getPristineRegs(MF);
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for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
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unsigned Reg = *I;
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if (!IsReturnBlock && !Pristine.test(Reg)) continue;
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@ -71,7 +71,7 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
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// all callee-saved registers. In non-return this is any
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// callee-saved register that is not saved in the prolog.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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BitVector Pristine = MFI->getPristineRegs(BB);
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BitVector Pristine = MFI->getPristineRegs(MF);
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for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
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if (!IsReturnBlock && !Pristine.test(*I)) continue;
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for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
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@ -584,12 +584,8 @@ int MachineFrameInfo::CreateFixedSpillStackObject(uint64_t Size,
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return -++NumFixedObjects;
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}
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BitVector
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MachineFrameInfo::getPristineRegs(const MachineBasicBlock *MBB) const {
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assert(MBB && "MBB must be valid");
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const MachineFunction *MF = MBB->getParent();
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assert(MF && "MBB must be part of a MachineFunction");
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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BitVector MachineFrameInfo::getPristineRegs(const MachineFunction &MF) const {
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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BitVector BV(TRI->getNumRegs());
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// Before CSI is calculated, no registers are considered pristine. They can be
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@ -597,14 +593,10 @@ MachineFrameInfo::getPristineRegs(const MachineBasicBlock *MBB) const {
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if (!isCalleeSavedInfoValid())
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return BV;
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for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR)
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for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
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BV.set(*CSR);
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// Each MBB before the save point has all CSRs pristine.
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if (isBeforeSavePoint(*MF, *MBB))
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return BV;
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// On other MBBs the saved CSRs are not pristine.
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// Saved CSRs are not pristine.
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const std::vector<CalleeSavedInfo> &CSI = getCalleeSavedInfo();
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I)
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@ -613,40 +605,6 @@ MachineFrameInfo::getPristineRegs(const MachineBasicBlock *MBB) const {
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return BV;
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}
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// Note: We could use some sort of caching mecanism, but we lack the ability
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// to know when the cache is invalid, i.e., the CFG changed.
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// Assuming we have that, we can simply compute all the set of MBBs
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// that are before the save point.
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bool MachineFrameInfo::isBeforeSavePoint(const MachineFunction &MF,
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const MachineBasicBlock &MBB) const {
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// Early exit if shrink-wrapping did not kick.
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if (!Save)
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return &MBB == &MF.front();
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// Starting from MBB, check if there is a path leading to Save that do
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// not cross Restore.
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SmallPtrSet<const MachineBasicBlock *, 8> Visited;
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SmallVector<const MachineBasicBlock *, 8> WorkList;
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WorkList.push_back(&MBB);
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Visited.insert(&MBB);
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do {
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const MachineBasicBlock *CurBB = WorkList.pop_back_val();
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// By construction, the region that is after the save point is
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// dominated by the Save and post-dominated by the Restore.
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// If we do not reach Restore and still reach Save, this
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// means MBB is before Save.
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if (CurBB == Save)
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return true;
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if (CurBB == Restore)
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continue;
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// Enqueue all the successors not already visited.
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for (MachineBasicBlock *SuccBB : CurBB->successors())
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if (Visited.insert(SuccBB).second)
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WorkList.push_back(SuccBB);
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} while (!WorkList.empty());
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return false;
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}
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unsigned MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
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@ -694,7 +694,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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assert(MFI && "Function has no frame info");
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BitVector PR = MFI->getPristineRegs(MBB);
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BitVector PR = MFI->getPristineRegs(*MF);
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for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
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for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
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SubRegs.isValid(); ++SubRegs)
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@ -55,7 +55,8 @@ void RegScavenger::initRegState() {
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setRegUsed(*I);
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// Pristine CSRs are also unavailable.
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BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
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const MachineFunction &MF = *MBB->getParent();
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BitVector PR = MF.getFrameInfo()->getPristineRegs(MF);
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for (int I = PR.find_first(); I>0; I = PR.find_next(I))
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setRegUsed(I);
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}
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