forked from OSchip/llvm-project
parent
8d922aa746
commit
1108ab059c
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@ -8578,7 +8578,7 @@ static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
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// Get widened type and narrowed type.
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MVT widenType;
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unsigned numElem = VT.getVectorNumElements();
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EVT inputLaneType = Vec.getValueType().getVectorElementType();
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switch (inputLaneType.getSimpleVT().SimpleTy) {
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case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
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@ -10558,7 +10558,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
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} else {
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assert(CC == ARMCC::NE && "How can a CMPZ node not be EQ or NE?");
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}
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if (Op1->getOpcode() != ISD::OR)
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return SDValue();
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@ -10588,7 +10588,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
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SDLoc dl(X);
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EVT VT = X.getValueType();
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unsigned BitInX = AndC->getAPIntValue().logBase2();
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if (BitInX != 0) {
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// We must shift X first.
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X = DAG.getNode(ISD::SRL, dl, VT, X,
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