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More APInt-ification. 

llvm-svn: 48201
This commit is contained in:
Dan Gohman 2008-03-11 00:11:06 +00:00
parent 6aa4f515bb
commit 10f7d850cf
1 changed files with 7 additions and 7 deletions
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14
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -495,7 +495,7 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
if (!UseCP) { if (!UseCP) {
if (VT!=MVT::f64 && VT!=MVT::f32) if (VT!=MVT::f64 && VT!=MVT::f32)
assert(0 && "Invalid type expansion"); assert(0 && "Invalid type expansion");
return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
(VT == MVT::f64) ? MVT::i64 : MVT::i32); (VT == MVT::f64) ? MVT::i64 : MVT::i32);
} }
@ -2331,8 +2331,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
if (CFP->getValueType(0) == MVT::f32 && if (CFP->getValueType(0) == MVT::f32 &&
getTypeAction(MVT::i32) == Legal) { getTypeAction(MVT::i32) == Legal) {
Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). Tmp3 = DAG.getConstant(CFP->getValueAPF().
convertToAPInt().getZExtValue(), convertToAPInt().zextOrTrunc(32),
MVT::i32); MVT::i32);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment); SVOffset, isVolatile, Alignment);
@ -2341,7 +2341,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
// If this target supports 64-bit registers, do a single 64-bit store. // If this target supports 64-bit registers, do a single 64-bit store.
if (getTypeAction(MVT::i64) == Legal) { if (getTypeAction(MVT::i64) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
getZExtValue(), MVT::i64); zextOrTrunc(64), MVT::i64);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment); SVOffset, isVolatile, Alignment);
break; break;
@ -2349,9 +2349,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
// Otherwise, if the target supports 32-bit registers, use 2 32-bit // Otherwise, if the target supports 32-bit registers, use 2 32-bit
// stores. If the target supports neither 32- nor 64-bits, this // stores. If the target supports neither 32- nor 64-bits, this
// xform is certainly not worth it. // xform is certainly not worth it.
uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue(); const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32); SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32); SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi); if (TLI.isBigEndian()) std::swap(Lo, Hi);
Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),