forked from OSchip/llvm-project
[PowerPC 2/4] Little-endian adjustments for VSX insert/extract operations
For little endian, we need to make some straightforward adjustments in the code expansions for scalar_to_vector and vector_extract of v2f64. First, scalar_to_vector must place the scalar into vector element zero. However, our implementation of SUBREG_TO_REG will place it into big-element vector element zero (high-order bits), and for little endian we need it in the low-order bits. The LE implementation splats the high-order doubleword into the low-order doubleword. Second, the meaning of (vector_extract x, 0) and (vector_extract x, 1) must be reversed for similar reasons. A new test is added that tests code generation for insertelement and extractelement for both element 0 and element 1. It is disabled in this patch but enabled in patch 4/4, for reasons stated in the test. llvm-svn: 223788
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@ -793,6 +793,8 @@ def : InstAlias<"xxswapd $XT, $XB",
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(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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let Predicates = [IsBigEndian] in {
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def : Pat<(v2f64 (scalar_to_vector f64:$A)),
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(v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
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@ -800,6 +802,18 @@ def : Pat<(f64 (vector_extract v2f64:$S, 0)),
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(f64 (EXTRACT_SUBREG $S, sub_64))>;
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def : Pat<(f64 (vector_extract v2f64:$S, 1)),
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(f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
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}
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let Predicates = [IsLittleEndian] in {
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def : Pat<(v2f64 (scalar_to_vector f64:$A)),
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(v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
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(SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
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def : Pat<(f64 (vector_extract v2f64:$S, 0)),
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(f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
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def : Pat<(f64 (vector_extract v2f64:$S, 1)),
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(f64 (EXTRACT_SUBREG $S, sub_64))>;
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}
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// Additional fnmsub patterns: -a*c + b == -(a*c - b)
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def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
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