forked from OSchip/llvm-project
Resubmit r301309: [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler.
This patch reapplies r301309 with the fix to the MIR test to fix the assertion triggered by r301309. Had trimmed a little bit too much from the MIR! llvm-svn: 301317
This commit is contained in:
Andrew Ng
parent
ba01143193
commit
10ebfe0684
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@ -964,10 +964,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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// sure to update that as well.
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const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
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if (!SU) continue;
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for (DbgValueVector::iterator DVI = DbgValues.begin(),
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DVE = DbgValues.end(); DVI != DVE; ++DVI)
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if (DVI->second == Q.second.Operand->getParent())
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UpdateDbgValue(*DVI->first, AntiDepReg, NewReg);
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UpdateDbgValues(DbgValues, Q.second.Operand->getParent(),
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AntiDepReg, NewReg);
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}
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// We just went back in time and modified history; the
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@ -60,6 +60,25 @@ public:
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if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
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MI.getOperand(0).setReg(NewReg);
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}
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/// Update all DBG_VALUE instructions that may be affected by the dependency
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/// breaker's update of ParentMI to use NewReg.
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void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
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unsigned OldReg, unsigned NewReg) {
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// The following code is dependent on the order in which the DbgValues are
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// constructed in ScheduleDAGInstrs::buildSchedGraph.
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MachineInstr *PrevDbgMI = nullptr;
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for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) {
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MachineInstr *PrevMI = DV.second;
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if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) {
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MachineInstr *DbgMI = DV.first;
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UpdateDbgValue(*DbgMI, OldReg, NewReg);
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PrevDbgMI = DbgMI;
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} else if (PrevDbgMI) {
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break; // If no match and already found a DBG_VALUE, we're done.
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}
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}
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}
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};
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}
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@ -648,10 +648,8 @@ BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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// as well.
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const SUnit *SU = MISUnitMap[Q->second->getParent()];
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if (!SU) continue;
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for (DbgValueVector::iterator DVI = DbgValues.begin(),
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DVE = DbgValues.end(); DVI != DVE; ++DVI)
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if (DVI->second == Q->second->getParent())
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UpdateDbgValue(*DVI->first, AntiDepReg, NewReg);
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UpdateDbgValues(DbgValues, Q->second->getParent(),
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AntiDepReg, NewReg);
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}
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// We just went back in time and modified history; the
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@ -0,0 +1,322 @@
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# RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=btver2 -run-pass=post-RA-sched -o - %s | FileCheck %s
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# Test that multiple DBG_VALUE's following an instruction whose register needs
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# to be changed during the post-RA scheduler pass are updated correctly.
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# Test case was derived from the output from the following command and
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# the source code below:
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#
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# clang -S -emit-llvm -target x86_64 -march=btver2 -O2 -g -o - <srcfile> |
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# llc -stop-before=post-RA-sched -o -
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#
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# Source code reduced from the original 8MB source file:
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#
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# struct a;
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# class b {
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# public:
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# a *c = ap;
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# unsigned *d() { return (unsigned *)c; }
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# a *ap;
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# };
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# enum { e = 2 };
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# template <typename f> f *g(f *h, f *i) {
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# long j = long(i), k = -!h;
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# return reinterpret_cast<f *>(long(h) | k & j);
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# }
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# class l {
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# public:
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# l(int);
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# int m;
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# };
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# unsigned *n;
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# unsigned o;
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# class p {
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# public:
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# int aa();
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# unsigned *q() {
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# n = r.d();
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# return g(n, &o);
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# }
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# b r;
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# };
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# class s : l {
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# public:
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# p t;
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# s(int h) : l(h), ab(t), ac(~0 << h) { ae(); }
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# p &ab;
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# int ac;
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# void ae() {
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# const unsigned *v;
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# const unsigned u = 0;
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# v = ab.q();
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# const unsigned *x = g(v, &u);
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# int w = x[m] & ac;
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# while (w) {
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# int z = (ab.aa() - 1) / e;
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# if (m <= z)
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# return;
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# }
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# }
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# };
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# class ad {
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# public:
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# ~ad() {
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# for (y();;)
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# ;
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# }
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# class y {
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# public:
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# y() : af(0) {}
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# s af;
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# };
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# };
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# class ag {
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# ad ah;
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# };
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# enum ai {};
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# class aj {
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# public:
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# aj(unsigned(ai));
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# ag ak;
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# };
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# struct al {
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# static unsigned am(ai);
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# };
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# template <int> struct an : al { static aj ao; };
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# template <> aj an<0>::ao(am);
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--- |
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%class.s = type <{ %class.l, [4 x i8], %class.p, %class.p*, i32, [4 x i8] }>
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%class.l = type { i32 }
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%class.p = type { %class.b }
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%class.b = type { %struct.a*, %struct.a* }
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%struct.a = type opaque
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@n = local_unnamed_addr global i32* null, align 8
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@o = global i32 0, align 4
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define linkonce_odr void @_ZN1sC2Ei(%class.s*, i32) unnamed_addr #0 align 2 !dbg !4 {
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%3 = alloca i32, align 4
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%4 = bitcast %class.s* %0 to %class.l*
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tail call void @_ZN1lC2Ei(%class.l* %4, i32 %1)
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%5 = getelementptr inbounds %class.s, %class.s* %0, i64 0, i32 2
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tail call void @llvm.dbg.value(metadata %class.p* %5, i64 0, metadata !10, metadata !17), !dbg !18
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tail call void @llvm.dbg.value(metadata %class.p* %5, i64 0, metadata !20, metadata !17), !dbg !27
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%6 = getelementptr inbounds %class.s, %class.s* %0, i64 0, i32 2, i32 0, i32 1
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%7 = bitcast %struct.a** %6 to i64*
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%8 = load i64, i64* %7, align 8
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%9 = bitcast %class.p* %5 to i64*
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store i64 %8, i64* %9, align 8
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%10 = getelementptr inbounds %class.s, %class.s* %0, i64 0, i32 3
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store %class.p* %5, %class.p** %10, align 8
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%11 = getelementptr inbounds %class.s, %class.s* %0, i64 0, i32 4
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%12 = shl i32 -1, %1
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store i32 %12, i32* %11, align 8
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store i32 0, i32* %3, align 4
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%13 = bitcast %class.p* %5 to i32**
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%14 = load i32*, i32** %13, align 8
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store i32* %14, i32** @n, align 8
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%15 = icmp eq i32* %14, null
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%16 = ptrtoint i32* %14 to i64
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%17 = select i1 %15, i64 ptrtoint (i32* @o to i64), i64 0
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%18 = or i64 %17, %16
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tail call void @llvm.dbg.value(metadata i32* %3, i64 0, metadata !29, metadata !35), !dbg !36
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tail call void @llvm.dbg.value(metadata i32* %3, i64 0, metadata !39, metadata !17), !dbg !44
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%19 = ptrtoint i32* %3 to i64
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call void @llvm.dbg.value(metadata i64 %19, i64 0, metadata !46, metadata !17), !dbg !48
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%20 = icmp eq i64 %18, 0
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%21 = select i1 %20, i64 %19, i64 0
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%22 = or i64 %21, %18
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%23 = inttoptr i64 %22 to i32*
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%24 = bitcast %class.s* %0 to i32*
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%25 = load i32, i32* %24, align 8
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%26 = sext i32 %25 to i64
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%27 = getelementptr inbounds i32, i32* %23, i64 %26
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%28 = load i32, i32* %27, align 4
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%29 = and i32 %12, %28
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%30 = icmp eq i32 %29, 0
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br i1 %30, label %47, label %31
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; <label>:31: ; preds = %2
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%32 = bitcast %class.s* %0 to i32*
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%33 = call i32 @_ZN1p2aaEv(%class.p* %5)
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%34 = add nsw i32 %33, -1
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%35 = sdiv i32 %34, 2
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%36 = load i32, i32* %32, align 8
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%37 = icmp sgt i32 %36, %35
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br i1 %37, label %38, label %47
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; <label>:38: ; preds = %31
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br label %39
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; <label>:39: ; preds = %39, %38
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%40 = bitcast %class.s* %0 to i32*
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%sunkaddr = ptrtoint %class.s* %0 to i64
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%sunkaddr1 = add i64 %sunkaddr, 24
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%sunkaddr2 = inttoptr i64 %sunkaddr1 to %class.p**
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%41 = load %class.p*, %class.p** %sunkaddr2, align 8
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%42 = call i32 @_ZN1p2aaEv(%class.p* %41)
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%43 = add nsw i32 %42, -1
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%44 = sdiv i32 %43, 2
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%45 = load i32, i32* %40, align 8
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%46 = icmp sgt i32 %45, %44
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br i1 %46, label %39, label %47
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; <label>:47: ; preds = %39, %31, %2
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ret void
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}
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declare void @_ZN1lC2Ei(%class.l*, i32) unnamed_addr #1
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declare i32 @_ZN1p2aaEv(%class.p*) local_unnamed_addr #1
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; Function Attrs: nounwind readnone
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declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!2, !3}
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!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
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!1 = !DIFile(filename: "test.cpp", directory: "")
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!2 = !{i32 2, !"Dwarf Version", i32 4}
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!3 = !{i32 2, !"Debug Info Version", i32 3}
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!4 = distinct !DISubprogram(name: "s", linkageName: "_ZN1sC2Ei", scope: !5, file: !1, line: 32, type: !6, isLocal: false, isDefinition: true, scopeLine: 32, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
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!5 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "s", file: !1, line: 29, size: 320, identifier: "_ZTS1s")
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!6 = !DISubroutineType(types: !7)
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!7 = !{null, !8, !9}
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!8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !5, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
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!9 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
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!10 = !DILocalVariable(name: "this", arg: 1, scope: !11, type: !16, flags: DIFlagArtificial | DIFlagObjectPointer)
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!11 = distinct !DISubprogram(name: "p", linkageName: "_ZN1pC2Ev", scope: !12, file: !1, line: 20, type: !13, isLocal: false, isDefinition: true, scopeLine: 20, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: true, unit: !0)
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!12 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "p", file: !1, line: 20, size: 128, identifier: "_ZTS1p")
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!13 = !DISubroutineType(types: !14)
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!14 = !{null, !15}
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!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
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!16 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64)
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!17 = !DIExpression()
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!18 = !DILocation(line: 0, scope: !11, inlinedAt: !19)
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!19 = distinct !DILocation(line: 32, column: 3, scope: !4)
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!20 = !DILocalVariable(name: "this", arg: 1, scope: !21, type: !26, flags: DIFlagArtificial | DIFlagObjectPointer)
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!21 = distinct !DISubprogram(name: "b", linkageName: "_ZN1bC2Ev", scope: !22, file: !1, line: 2, type: !23, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagArtificial | DIFlagPrototyped, isOptimized: true, unit: !0)
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!22 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "b", file: !1, line: 2, size: 128, identifier: "_ZTS1b")
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!23 = !DISubroutineType(types: !24)
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!24 = !{null, !25}
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!25 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !22, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
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!26 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !22, size: 64)
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!27 = !DILocation(line: 0, scope: !21, inlinedAt: !28)
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!28 = distinct !DILocation(line: 20, column: 7, scope: !11, inlinedAt: !19)
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!29 = !DILocalVariable(name: "u", scope: !30, file: !1, line: 37, type: !33)
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!30 = distinct !DISubprogram(name: "ae", linkageName: "_ZN1s2aeEv", scope: !5, file: !1, line: 35, type: !31, isLocal: false, isDefinition: true, scopeLine: 35, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
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!31 = !DISubroutineType(types: !32)
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!32 = !{null, !8}
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!33 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !34)
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!34 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
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!35 = !DIExpression(DW_OP_deref)
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!36 = !DILocation(line: 37, column: 20, scope: !30, inlinedAt: !37)
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!37 = distinct !DILocation(line: 32, column: 41, scope: !38)
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!38 = distinct !DILexicalBlock(scope: !4, file: !1, line: 32, column: 39)
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!39 = !DILocalVariable(name: "i", arg: 2, scope: !40, file: !1, line: 9, type: !43)
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!40 = distinct !DISubprogram(name: "g<const unsigned int>", linkageName: "_Z1gIKjEPT_S2_S2_", scope: !1, file: !1, line: 9, type: !41, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
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!41 = !DISubroutineType(types: !42)
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!42 = !{!43, !43, !43}
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!43 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !33, size: 64)
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!44 = !DILocation(line: 9, column: 37, scope: !40, inlinedAt: !45)
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!45 = distinct !DILocation(line: 39, column: 25, scope: !30, inlinedAt: !37)
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!46 = !DILocalVariable(name: "j", scope: !40, file: !1, line: 10, type: !47)
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!47 = !DIBasicType(name: "long int", size: 64, encoding: DW_ATE_signed)
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!48 = !DILocation(line: 10, column: 8, scope: !40, inlinedAt: !45)
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...
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---
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name: _ZN1sC2Ei
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tracksRegLiveness: true
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liveins:
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- { reg: '%rdi' }
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- { reg: '%esi' }
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fixedStack:
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- { id: 0, type: spill-slot, offset: -32, size: 8, alignment: 16, callee-saved-register: '%rbx' }
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- { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%r14' }
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- { id: 2, type: spill-slot, offset: -16, size: 8, alignment: 16 }
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stack:
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- { id: 0, offset: -36, size: 4, alignment: 4 }
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body: |
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bb.0:
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successors: %bb.3, %bb.2
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liveins: %esi, %rdi, %r14, %rbx, %rbp
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; CHECK: [[REGISTER:%r[a-z0-9]+]] = LEA64r {{%r[a-z0-9]+}}, 1, _, -20, _
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; CHECK-NEXT: DBG_VALUE debug-use [[REGISTER]], debug-use _, !46, !17, debug-location !48
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; CHECK-NEXT: DBG_VALUE debug-use [[REGISTER]], debug-use _, !39, !17, debug-location !44
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frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
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CFI_INSTRUCTION def_cfa_offset 16
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CFI_INSTRUCTION offset %rbp, -16
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%rbp = frame-setup MOV64rr %rsp
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CFI_INSTRUCTION def_cfa_register %rbp
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frame-setup PUSH64r killed %r14, implicit-def %rsp, implicit %rsp
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frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
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%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
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CFI_INSTRUCTION offset %rbx, -32
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CFI_INSTRUCTION offset %r14, -24
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%r14d = MOV32rr %esi
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%rbx = MOV64rr %rdi
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CALL64pcrel32 @_ZN1lC2Ei, csr_64, implicit %rsp, implicit %rdi, implicit %esi, implicit-def %rsp
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%rdi = LEA64r %rbx, 1, _, 8, _
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DBG_VALUE debug-use %rdi, debug-use _, !20, !17, debug-location !27
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DBG_VALUE debug-use %rdi, debug-use _, !10, !17, debug-location !18
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%rax = MOV64rm %rbx, 1, _, 16, _ :: (load 8)
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MOV64mr %rbx, 1, _, 8, _, killed %rax :: (store 8)
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MOV64mr %rbx, 1, _, 24, _, %rdi :: (store 8)
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%eax = MOV32ri -1
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%cl = MOV8rr %r14b, implicit killed %r14d
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%eax = SHL32rCL killed %eax, implicit-def dead %eflags, implicit %cl
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MOV32mr %rbx, 1, _, 32, _, %eax :: (store 4, align 8)
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MOV32mi %rbp, 1, _, -20, _, 0 :: (store 4)
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%rcx = MOV64rm %rbx, 1, _, 8, _ :: (load 8)
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MOV64mr %rip, 1, _, @n, _, %rcx :: (store 8)
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%edx = XOR32rr undef %edx, undef %edx, implicit-def dead %eflags, implicit-def %rdx
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TEST64rr %rcx, %rcx, implicit-def %eflags
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%esi = MOV32ri @o, implicit-def %rsi
|
||||
%rsi = CMOVNE64rr killed %rsi, %rdx, implicit killed %eflags
|
||||
%rsi = OR64rr killed %rsi, killed %rcx, implicit-def %eflags
|
||||
%rcx = LEA64r %rbp, 1, _, -20, _
|
||||
DBG_VALUE debug-use %rcx, debug-use _, !46, !17, debug-location !48
|
||||
DBG_VALUE debug-use %rcx, debug-use _, !39, !17, debug-location !44
|
||||
DBG_VALUE %rbp, -20, !29, !17, debug-location !36
|
||||
%rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags
|
||||
%rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags
|
||||
%rdx = MOVSX64rm32 %rbx, 1, _, 0, _ :: (load 4, align 8)
|
||||
TEST32rm killed %eax, killed %rcx, 4, killed %rdx, 0, _, implicit-def %eflags :: (load 4)
|
||||
JNE_1 %bb.2, implicit %eflags
|
||||
JMP_1 %bb.3
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
liveins: %rbx, %rbp
|
||||
|
||||
%rdi = MOV64rm %rbx, 1, _, 24, _ :: (load 8)
|
||||
|
||||
bb.2:
|
||||
successors: %bb.1, %bb.3
|
||||
liveins: %rbx, %rbp, %rsp, %rdi
|
||||
|
||||
CALL64pcrel32 @_ZN1p2aaEv, csr_64, implicit %rsp, implicit %rdi, implicit-def %rsp, implicit-def %eax
|
||||
%eax = KILL %eax, implicit-def %rax
|
||||
%ecx = LEA64_32r %rax, 1, _, -1, _, implicit-def %rcx
|
||||
%ecx = SHR32ri %ecx, 31, implicit-def dead %eflags, implicit killed %rcx, implicit-def %rcx
|
||||
%eax = LEA64_32r killed %rax, 1, killed %rcx, -1, _
|
||||
%eax = SAR32r1 killed %eax, implicit-def dead %eflags
|
||||
CMP32mr %rbx, 1, _, 0, _, killed %eax, implicit-def %eflags :: (load 4, align 8), (load 4, align 8)
|
||||
JG_1 %bb.1, implicit killed %eflags
|
||||
|
||||
bb.3:
|
||||
liveins: %rbp
|
||||
|
||||
%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
|
||||
%rbx = POP64r implicit-def %rsp, implicit %rsp
|
||||
%r14 = POP64r implicit-def %rsp, implicit %rsp
|
||||
%rbp = POP64r implicit-def %rsp, implicit %rsp
|
||||
RETQ
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue