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remove support for llvm.isunordered 

llvm-svn: 32992
This commit is contained in:
Chris Lattner 2007-01-07 08:37:22 +00:00
parent d0c91e1c2e
commit 10cae15d8e
1 changed files with 0 additions and 22 deletions
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22
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -843,22 +843,6 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond,
!InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
const BasicBlock *BB = CurBB->getBasicBlock(); const BasicBlock *BB = CurBB->getBasicBlock();
if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Cond))
if ((II->getIntrinsicID() == Intrinsic::isunordered_f32 ||
II->getIntrinsicID() == Intrinsic::isunordered_f64) &&
// The operands of the setcc have to be in this block. We don't know
// how to export them from some other block. If this is the first
// block of the sequence, no exporting is needed.
(CurBB == CurMBB ||
(isExportableFromCurrentBlock(II->getOperand(1), BB) &&
isExportableFromCurrentBlock(II->getOperand(2), BB)))) {
SelectionDAGISel::CaseBlock CB(ISD::SETUO, II->getOperand(1),
II->getOperand(2), TBB, FBB, CurBB);
SwitchCases.push_back(CB);
return;
}
// If the leaf of the tree is a comparison, merge the condition into // If the leaf of the tree is a comparison, merge the condition into
// the caseblock. // the caseblock.
if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) && if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
@ -2038,12 +2022,6 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0; return 0;
} }
case Intrinsic::isunordered_f32:
case Intrinsic::isunordered_f64:
setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
getValue(I.getOperand(2)), ISD::SETUO));
return 0;
case Intrinsic::sqrt_f32: case Intrinsic::sqrt_f32:
case Intrinsic::sqrt_f64: case Intrinsic::sqrt_f64:
setValue(&I, DAG.getNode(ISD::FSQRT, setValue(&I, DAG.getNode(ISD::FSQRT,