maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

When tracking demanded bits, if any bits from the sext of an SRA are demanded, 

then so is the input sign bit.  This fixes mediabench/g721 on X86.

llvm-svn: 28166
This commit is contained in:
Chris Lattner 2006-05-08 17:22:53 +00:00
parent d7a19102d1
commit 10c653744e
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
llvm/lib/Target/TargetLowering.cpp
View File

@ -467,8 +467,14 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
uint64_t TypeMask = MVT::getIntVTBitMask(VT);
if (SimplifyDemandedBits(Op.getOperand(0),
(DemandedMask << ShAmt) & TypeMask,
uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
// If any of the demanded bits are produced by the sign extension, we also
// demand the input sign bit.
if (HighBits & DemandedMask)
InDemandedMask |= MVT::getIntVTSignBit(VT);
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
KnownZero, KnownOne, TLO, Depth+1))
return true;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");