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Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 

llvm-svn: 28104
This commit is contained in:
Chris Lattner 2006-05-04 18:05:43 +00:00
parent 700cd27e83
commit 10b71c0d08
11 changed files with 37 additions and 52 deletions
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45
llvm/include/llvm/CodeGen/MachineInstr.h
View File

@ -61,7 +61,7 @@ public:
};
enum MachineOperandType {
MO_VirtualRegister, // virtual register for *value
MO_Register, // Register operand.
MO_Immediate, // Immediate Operand
MO_MachineBasicBlock, // MachineBasicBlock reference
MO_FrameIndex, // Abstract Stack Frame Index
@ -93,12 +93,17 @@ private:
extra.offset = 0;
}
MachineOperand(int64_t ImmVal, MachineOperandType OpTy, int Offset = 0)
: flags(0), opType(OpTy) {
MachineOperand(int64_t ImmVal) : flags(0), opType(MO_Immediate) {
contents.immedVal = ImmVal;
extra.offset = Offset;
extra.offset = 0;
}
MachineOperand(unsigned Idx, MachineOperandType OpTy)
: flags(0), opType(OpTy) {
contents.immedVal = Idx;
extra.offset = 0;
}
MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy)
: flags(UseTy), opType(OpTy) {
zeroContents();
@ -152,7 +157,7 @@ public:
/// Accessors that tell you what kind of MachineOperand you're looking at.
///
bool isRegister() const { return opType == MO_VirtualRegister; }
bool isRegister() const { return opType == MO_Register; }
bool isImmediate() const { return opType == MO_Immediate; }
bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
bool isFrameIndex() const { return opType == MO_FrameIndex; }
@ -245,7 +250,7 @@ public:
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
void ChangeToRegister(unsigned Reg) {
opType = MO_VirtualRegister;
opType = MO_Register;
extra.regNum = Reg;
}
@ -353,16 +358,6 @@ public:
// Accessors to add operands when building up machine instructions
//
/// addRegOperand - Add a symbolic virtual register reference...
///
void addRegOperand(int reg, bool isDef) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
MachineOperand(reg, MachineOperand::MO_VirtualRegister,
isDef ? MachineOperand::Def : MachineOperand::Use));
}
/// addRegOperand - Add a symbolic virtual register reference...
///
void addRegOperand(int reg,
@ -370,26 +365,16 @@ public:
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy));
MachineOperand(reg, MachineOperand::MO_Register, UTy));
}
/// addZeroExtImmOperand - Add a zero extended constant argument to the
/// addImmOperand - Add a zero extended constant argument to the
/// machine instruction.
///
void addZeroExtImmOperand(int intValue) {
void addImmOperand(int64_t Val) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
MachineOperand(intValue, MachineOperand::MO_Immediate));
}
/// addZeroExtImm64Operand - Add a zero extended 64-bit constant argument
/// to the machine instruction.
///
void addZeroExtImm64Operand(uint64_t intValue) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(intValue, MachineOperand::MO_Immediate));
operands.push_back(MachineOperand(Val));
}
void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {

8
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -42,22 +42,22 @@ public:
/// addImm - Add a new immediate operand.
///
const MachineInstrBuilder &addImm(int Val) const {
MI->addZeroExtImmOperand(Val);
const MachineInstrBuilder &addImm(int64_t Val) const {
MI->addImmOperand(Val);
return *this;
}
/// addZImm - Add a new zero extended immediate operand...
///
const MachineInstrBuilder &addZImm(unsigned Val) const {
MI->addZeroExtImmOperand(Val);
MI->addImmOperand(Val);
return *this;
}
/// addImm64 - Add a new 64-bit immediate operand...
///
const MachineInstrBuilder &addImm64(uint64_t Val) const {
MI->addZeroExtImm64Operand(Val);
MI->addImmOperand(Val);
return *this;
}

4
llvm/lib/CodeGen/MachineInstr.cpp
View File

@ -138,7 +138,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
if (TM) MRI = TM->getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_Register:
OutputReg(OS, MO.getReg(), MRI);
break;
case MachineOperand::MO_Immediate:
@ -235,7 +235,7 @@ std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_Register:
OutputReg(OS, MO.getReg());
break;
case MachineOperand::MO_Immediate:

6
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -104,7 +104,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
}
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op)) {
MI->addZeroExtImm64Operand(C->getValue());
MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) {
MI->addRegOperand(R->getReg(), MachineOperand::Use);
@ -303,7 +303,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
unsigned NumVals = Flags >> 3;
MI->addZeroExtImm64Operand(Flags);
MI->addImmOperand(Flags);
++i; // Skip the ID value.
switch (Flags & 7) {
@ -323,7 +323,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
case 3: { // Immediate.
assert(NumVals == 1 && "Unknown immediate value!");
uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
MI->addZeroExtImm64Operand(Val);
MI->addImmOperand(Val);
++i;
break;
}

4
llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
View File

@ -77,7 +77,7 @@ FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
{
const MachineOperand &MO = MI->getOperand(opNum);
if (MO.getType() == MachineOperand::MO_VirtualRegister) {
if (MO.getType() == MachineOperand::MO_Register) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
@ -93,7 +93,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
int new_symbol;
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_Register:
O << RI.get(MO.getReg()).Name;
return;

4
llvm/lib/Target/IA64/IA64AsmPrinter.cpp
View File

@ -66,7 +66,7 @@ namespace {
// This method is used by the tablegen'erated instruction printer.
void printOperand(const MachineInstr *MI, unsigned OpNo){
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_VirtualRegister) {
if (MO.getType() == MachineOperand::MO_Register) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
//XXX Bug Workaround: See note in Printer::doInitialization about %.
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
@ -173,7 +173,7 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
bool isBRCALLinsn /* = false */) {
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_Register:
O << RI.get(MO.getReg()).Name;
return;

2
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -86,7 +86,7 @@ namespace {
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_VirtualRegister) {
if (MO.isRegister()) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {

10
llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -146,7 +146,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
CloseParen = true;
}
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_Register:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
else
@ -188,16 +188,16 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
if (OpTy == MachineOperand::MO_VirtualRegister &&
if (MI->getOperand(opNum+1).isRegister() &&
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
if (OpTy == MachineOperand::MO_Immediate &&
if (MI->getOperand(opNum+1).isImmediate() &&
MI->getOperand(opNum+1).getImmedValue() == 0)
return; // don't print "+0"
O << "+";
if (OpTy == MachineOperand::MO_GlobalAddress ||
OpTy == MachineOperand::MO_ConstantPoolIndex) {
if (MI->getOperand(opNum+1).isGlobalAddress() ||
MI->getOperand(opNum+1).isConstantPoolIndex()) {
O << "%lo(";
printOperand(MI, opNum+1);
O << ")";

2
llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
View File

@ -108,7 +108,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
const MachineOperand &MO = MI->getOperand(OpNo);
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_Register:
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
O << '%';

2
llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
View File

@ -100,7 +100,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) {
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_Register:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << RI.get(MO.getReg()).Name;
else

2
llvm/lib/Target/X86/X86IntelAsmPrinter.h
View File

@ -37,7 +37,7 @@ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
void printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier = 0) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_VirtualRegister) {
if (MO.isRegister()) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else {