forked from OSchip/llvm-project
AArch64: Resolve some FIXMEs in CGBuiltin left over from backend merge
Merge vrshr_n_v and vqshlu_n_v with ARM. Remove FIXME comments for others as they can't actually be shared. NFC. Differential Revision: http://reviews.llvm.org/D4697 llvm-svn: 214173
This commit is contained in:
Yi Kong
parent
2b5f3f0124
commit
1083eb5c11
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@ -2040,6 +2040,8 @@ static NeonIntrinsicInfo ARMSIMDIntrinsicMap [] = {
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NEONMAP2(vqshl_v, arm_neon_vqshiftu, arm_neon_vqshifts, Add1ArgType | UnsignedAlts),
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NEONMAP2(vqshlq_n_v, arm_neon_vqshiftu, arm_neon_vqshifts, UnsignedAlts),
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NEONMAP2(vqshlq_v, arm_neon_vqshiftu, arm_neon_vqshifts, Add1ArgType | UnsignedAlts),
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NEONMAP1(vqshlu_n_v, arm_neon_vqshiftsu, 0),
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NEONMAP1(vqshluq_n_v, arm_neon_vqshiftsu, 0),
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NEONMAP2(vqsub_v, arm_neon_vqsubu, arm_neon_vqsubs, Add1ArgType | UnsignedAlts),
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NEONMAP2(vqsubq_v, arm_neon_vqsubu, arm_neon_vqsubs, Add1ArgType | UnsignedAlts),
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NEONMAP1(vraddhn_v, arm_neon_vraddhn, Add1ArgType),
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@ -2051,6 +2053,8 @@ static NeonIntrinsicInfo ARMSIMDIntrinsicMap [] = {
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NEONMAP2(vrhaddq_v, arm_neon_vrhaddu, arm_neon_vrhadds, Add1ArgType | UnsignedAlts),
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NEONMAP2(vrshl_v, arm_neon_vrshiftu, arm_neon_vrshifts, Add1ArgType | UnsignedAlts),
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NEONMAP2(vrshlq_v, arm_neon_vrshiftu, arm_neon_vrshifts, Add1ArgType | UnsignedAlts),
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NEONMAP2(vrshr_n_v, arm_neon_vrshiftu, arm_neon_vrshifts, UnsignedAlts),
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NEONMAP2(vrshrq_n_v, arm_neon_vrshiftu, arm_neon_vrshifts, UnsignedAlts),
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NEONMAP2(vrsqrte_v, arm_neon_vrsqrte, arm_neon_vrsqrte, 0),
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NEONMAP2(vrsqrteq_v, arm_neon_vrsqrte, arm_neon_vrsqrte, 0),
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NEONMAP1(vrsqrts_v, arm_neon_vrsqrts, Add1ArgType),
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@ -2171,6 +2175,8 @@ static NeonIntrinsicInfo AArch64SIMDIntrinsicMap[] = {
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NEONMAP2(vqshl_v, aarch64_neon_uqshl, aarch64_neon_sqshl, Add1ArgType | UnsignedAlts),
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NEONMAP2(vqshlq_n_v, aarch64_neon_uqshl, aarch64_neon_sqshl,UnsignedAlts),
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NEONMAP2(vqshlq_v, aarch64_neon_uqshl, aarch64_neon_sqshl, Add1ArgType | UnsignedAlts),
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NEONMAP1(vqshlu_n_v, aarch64_neon_sqshlu, 0),
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NEONMAP1(vqshluq_n_v, aarch64_neon_sqshlu, 0),
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NEONMAP2(vqsub_v, aarch64_neon_uqsub, aarch64_neon_sqsub, Add1ArgType | UnsignedAlts),
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NEONMAP2(vqsubq_v, aarch64_neon_uqsub, aarch64_neon_sqsub, Add1ArgType | UnsignedAlts),
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NEONMAP1(vraddhn_v, aarch64_neon_raddhn, Add1ArgType),
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@ -2182,6 +2188,8 @@ static NeonIntrinsicInfo AArch64SIMDIntrinsicMap[] = {
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NEONMAP2(vrhaddq_v, aarch64_neon_urhadd, aarch64_neon_srhadd, Add1ArgType | UnsignedAlts),
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NEONMAP2(vrshl_v, aarch64_neon_urshl, aarch64_neon_srshl, Add1ArgType | UnsignedAlts),
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NEONMAP2(vrshlq_v, aarch64_neon_urshl, aarch64_neon_srshl, Add1ArgType | UnsignedAlts),
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NEONMAP2(vrshr_n_v, aarch64_neon_urshl, aarch64_neon_srshl, UnsignedAlts),
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NEONMAP2(vrshrq_n_v, aarch64_neon_urshl, aarch64_neon_srshl, UnsignedAlts),
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NEONMAP2(vrsqrte_v, aarch64_neon_frsqrte, aarch64_neon_ursqrte, 0),
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NEONMAP2(vrsqrteq_v, aarch64_neon_frsqrte, aarch64_neon_ursqrte, 0),
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NEONMAP1(vrsqrts_v, aarch64_neon_frsqrts, Add1ArgType),
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@ -2826,6 +2834,10 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr(
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case NEON::BI__builtin_neon_vqshlq_n_v:
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshl_n",
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1, false);
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case NEON::BI__builtin_neon_vqshlu_n_v:
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case NEON::BI__builtin_neon_vqshluq_n_v:
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshlu_n",
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1, false);
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case NEON::BI__builtin_neon_vrecpe_v:
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case NEON::BI__builtin_neon_vrecpeq_v:
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case NEON::BI__builtin_neon_vrsqrte_v:
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@ -2833,6 +2845,10 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr(
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Int = Ty->isFPOrFPVectorTy() ? LLVMIntrinsic : AltLLVMIntrinsic;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, NameHint);
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case NEON::BI__builtin_neon_vrshr_n_v:
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case NEON::BI__builtin_neon_vrshrq_n_v:
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshr_n",
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1, true);
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case NEON::BI__builtin_neon_vshl_n_v:
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case NEON::BI__builtin_neon_vshlq_n_v:
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Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false);
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@ -3498,10 +3514,6 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
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case NEON::BI__builtin_neon_vqrshrun_n_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrshiftnsu, Ty),
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Ops, "vqrshrun_n", 1, true);
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case NEON::BI__builtin_neon_vqshlu_n_v:
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case NEON::BI__builtin_neon_vqshluq_n_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftsu, Ty),
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Ops, "vqshlu", 1, false);
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case NEON::BI__builtin_neon_vqshrn_n_v:
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Int = usgn ? Intrinsic::arm_neon_vqshiftnu : Intrinsic::arm_neon_vqshiftns;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshrn_n",
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@ -3516,10 +3528,6 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
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case NEON::BI__builtin_neon_vrshrn_n_v:
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrshiftn, Ty),
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Ops, "vrshrn_n", 1, true);
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case NEON::BI__builtin_neon_vrshr_n_v:
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case NEON::BI__builtin_neon_vrshrq_n_v:
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Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshr_n", 1, true);
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case NEON::BI__builtin_neon_vrsra_n_v:
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case NEON::BI__builtin_neon_vrsraq_n_v:
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Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
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@ -4673,38 +4681,19 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::aarch64_neon_frecps, f64Type),
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Ops, "vrecps");
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}
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case NEON::BI__builtin_neon_vrshr_n_v:
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case NEON::BI__builtin_neon_vrshrq_n_v:
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// FIXME: this can be shared with 32-bit ARM, but not AArch64 at the
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// moment. After the final merge it should be added to
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// EmitCommonNeonBuiltinExpr.
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Int = usgn ? Intrinsic::aarch64_neon_urshl : Intrinsic::aarch64_neon_srshl;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshr_n", 1, true);
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case NEON::BI__builtin_neon_vqshlu_n_v:
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case NEON::BI__builtin_neon_vqshluq_n_v:
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// FIXME: AArch64 and ARM use different intrinsics for this, but are
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// essentially compatible. It should be in EmitCommonNeonBuiltinExpr after
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// the final merge.
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Int = Intrinsic::aarch64_neon_sqshlu;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshlu_n", 1, false);
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case NEON::BI__builtin_neon_vqshrun_n_v:
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// FIXME: as above
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Int = Intrinsic::aarch64_neon_sqshrun;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshrun_n");
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case NEON::BI__builtin_neon_vqrshrun_n_v:
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// FIXME: and again.
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Int = Intrinsic::aarch64_neon_sqrshrun;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqrshrun_n");
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case NEON::BI__builtin_neon_vqshrn_n_v:
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// FIXME: guess
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Int = usgn ? Intrinsic::aarch64_neon_uqshrn : Intrinsic::aarch64_neon_sqshrn;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshrn_n");
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case NEON::BI__builtin_neon_vrshrn_n_v:
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// FIXME: there might be a pattern here.
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Int = Intrinsic::aarch64_neon_rshrn;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshrn_n");
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case NEON::BI__builtin_neon_vqrshrn_n_v:
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// FIXME: another one
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Int = usgn ? Intrinsic::aarch64_neon_uqrshrn : Intrinsic::aarch64_neon_sqrshrn;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqrshrn_n");
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case NEON::BI__builtin_neon_vrnda_v:
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