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[AArch64] Fix optimizeCondBranch logic. 

The opcode for the optimized branch does not depend on the size
of the activate bits in the AND masks, but the AND opcode itself.
Indeed, we need to use a X or W variant based on the AND variant
not based on whether the mask fits into the related variant.
Otherwise, we may end up using the W variant of the optimized branch
for 64-bit register inputs!

This fixes the last make check verifier issues for AArch64: PR27479.

llvm-svn: 267206
This commit is contained in:
Quentin Colombet 2016-04-22 20:09:58 +00:00
parent 55a1d50b3a
commit 10768ab09e
2 changed files with 6 additions and 6 deletions
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10
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -3353,9 +3353,9 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr *MI) const {
if (!MRI->hasOneNonDBGUse(VReg))
return false;
bool Is64Bit = DefMI->getOpcode() != AArch64::ANDWri;
uint64_t Mask = AArch64_AM::decodeLogicalImmediate(
DefMI->getOperand(2).getImm(),
(DefMI->getOpcode() == AArch64::ANDWri) ? 32 : 64);
DefMI->getOperand(2).getImm(), Is64Bit ? 64 : 32);
if (!isPowerOf2_64(Mask))
return false;
@ -3370,9 +3370,9 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr *MI) const {
MachineBasicBlock *TBB = MI->getOperand(1).getMBB();
DebugLoc DL = MI->getDebugLoc();
unsigned Imm = Log2_64(Mask);
unsigned Opc = (Imm < 32)
? (IsNegativeBranch ? AArch64::TBNZW : AArch64::TBZW)
: (IsNegativeBranch ? AArch64::TBNZX : AArch64::TBZX);
unsigned Opc = Is64Bit
? (IsNegativeBranch ? AArch64::TBNZX : AArch64::TBZX)
: (IsNegativeBranch ? AArch64::TBNZW : AArch64::TBZW);
BuildMI(RefToMBB, MI, DL, get(Opc)).addReg(NewReg).addImm(Imm).addMBB(TBB);
MI->eraseFromParent();
return true;

2
llvm/test/CodeGen/AArch64/aarch64-tbz.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple=aarch64-linux-gnueabi < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnueabi < %s | FileCheck %s
; CHECK-LABEL: test1
; CHECK: tbz {{w[0-9]}}, #3, {{.LBB0_3}}