From 106dd035a8eda70d5a43dbe3a41911e951c11a79 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Tue, 12 Sep 2017 21:04:11 +0000
Subject: [PATCH] [AArch64][GlobalISel] Select all fpexts.

Tablegen already can select these: mark them as legal, remove the
c++ code, and add tests for all types.

llvm-svn: 313074
---
 .../AArch64/AArch64InstructionSelector.cpp    | 27 ---------
 .../Target/AArch64/AArch64LegalizerInfo.cpp   | 13 +++--
 .../AArch64/GlobalISel/select-fp-casts.mir    | 58 ++++++++++++++++++-
 3 files changed, 62 insertions(+), 36 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 9cf9cd8b8e2d..58624f24ec0f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1180,33 +1180,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
       return selectCopy(I, TII, MRI, TRI, RBI);
     return false;
 
-  case TargetOpcode::G_FPEXT: {
-    if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(64)) {
-      DEBUG(dbgs() << "G_FPEXT to type " << Ty
-                   << ", expected: " << LLT::scalar(64) << '\n');
-      return false;
-    }
-
-    if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(32)) {
-      DEBUG(dbgs() << "G_FPEXT from type " << Ty
-                   << ", expected: " << LLT::scalar(32) << '\n');
-      return false;
-    }
-
-    const unsigned DefReg = I.getOperand(0).getReg();
-    const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
-
-    if (RB.getID() != AArch64::FPRRegBankID) {
-      DEBUG(dbgs() << "G_FPEXT on bank: " << RB << ", expected: FPR\n");
-      return false;
-    }
-
-    I.setDesc(TII.get(AArch64::FCVTDSr));
-    constrainSelectedInstRegOperands(I, TII, TRI, RBI);
-
-    return true;
-  }
-
   case TargetOpcode::G_SELECT: {
     if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) {
       DEBUG(dbgs() << "G_SELECT cond has type: " << Ty
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index 9a86cac44b51..e28e43acba1b 100644
--- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -161,15 +161,16 @@ AArch64LegalizerInfo::AArch64LegalizerInfo() {
     setAction({G_ANYEXT, 1, Ty}, Legal);
   }
 
-  setAction({G_FPEXT, s64}, Legal);
-  setAction({G_FPEXT, 1, s32}, Legal);
-
-  // Truncations
-  for (auto Ty : { s16, s32 })
+  // FP conversions
+  for (auto Ty : { s16, s32 }) {
     setAction({G_FPTRUNC, Ty}, Legal);
+    setAction({G_FPEXT, 1, Ty}, Legal);
+  }
 
-  for (auto Ty : { s32, s64 })
+  for (auto Ty : { s32, s64 }) {
     setAction({G_FPTRUNC, 1, Ty}, Legal);
+    setAction({G_FPEXT, Ty}, Legal);
+  }
 
   for (auto Ty : { s1, s8, s16, s32 })
     setAction({G_TRUNC, Ty}, Legal);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
index d1a461107d8f..3c3431935577 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
@@ -7,7 +7,9 @@
   define void @fptrunc_s16_s64_fpr() { ret void }
   define void @fptrunc_s32_s64_fpr() { ret void }
 
-  define void @fpext() { ret void }
+  define void @fpext_s32_s16_fpr() { ret void }
+  define void @fpext_s64_s16_fpr() { ret void }
+  define void @fpext_s64_s32_fpr() { ret void }
 
   define void @sitofp_s32_s32_fpr() { ret void }
   define void @sitofp_s32_s64_fpr() { ret void }
@@ -106,8 +108,58 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: fpext
-name:            fpext
+# CHECK-LABEL: name: fpext_s32_s16_fpr
+name:            fpext_s32_s16_fpr
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK: - { id: 0, class: fpr16, preferred-register: '' }
+# CHECK: - { id: 1, class: fpr32, preferred-register: '' }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %h0
+# CHECK:    %1 = FCVTSHr %0
+body:             |
+  bb.0:
+    liveins: %h0
+
+    %0(s16) = COPY %h0
+    %1(s32) = G_FPEXT %0
+    %s0 = COPY %1(s32)
+...
+
+---
+# CHECK-LABEL: name: fpext_s64_s16_fpr
+name:            fpext_s64_s16_fpr
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK: - { id: 0, class: fpr16, preferred-register: '' }
+# CHECK: - { id: 1, class: fpr64, preferred-register: '' }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %h0
+# CHECK:    %1 = FCVTDHr %0
+body:             |
+  bb.0:
+    liveins: %h0
+
+    %0(s16) = COPY %h0
+    %1(s64) = G_FPEXT %0
+    %d0 = COPY %1(s64)
+...
+
+---
+# CHECK-LABEL: name: fpext_s64_s32_fpr
+name:            fpext_s64_s32_fpr
 legalized:       true
 regBankSelected: true