forked from OSchip/llvm-project
R600/SI: Handle physical registers in getOpRegClass
llvm-svn: 224079
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@ -1242,8 +1242,13 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
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const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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const MCInstrDesc &Desc = get(MI.getOpcode());
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const MCInstrDesc &Desc = get(MI.getOpcode());
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if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
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if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
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Desc.OpInfo[OpNo].RegClass == -1)
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Desc.OpInfo[OpNo].RegClass == -1) {
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return MRI.getRegClass(MI.getOperand(OpNo).getReg());
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unsigned Reg = MI.getOperand(OpNo).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return MRI.getRegClass(Reg);
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return RI.getRegClass(Reg);
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}
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unsigned RCID = Desc.OpInfo[OpNo].RegClass;
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unsigned RCID = Desc.OpInfo[OpNo].RegClass;
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return RI.getRegClass(RCID);
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return RI.getRegClass(RCID);
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