forked from OSchip/llvm-project
X86ISelLowering.cpp - remove non-constant EXTRACT_SUBVECTOR/INSERT_SUBVECTOR handling. NFC.
Now that D79814 has landed, we can assume that subvector ops use constant, in-range indices.
This commit is contained in:
Simon Pilgrim
parent
36b9b1e617
commit
1024e82469
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@ -5786,8 +5786,7 @@ static bool collectConcatOps(SDNode *N, SmallVectorImpl<SDValue> &Ops) {
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return true;
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}
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if (N->getOpcode() == ISD::INSERT_SUBVECTOR &&
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isa<ConstantSDNode>(N->getOperand(2))) {
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if (N->getOpcode() == ISD::INSERT_SUBVECTOR) {
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SDValue Src = N->getOperand(0);
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SDValue Sub = N->getOperand(1);
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const APInt &Idx = N->getConstantOperandAPInt(2);
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@ -5939,21 +5938,17 @@ static SDValue insert1BitVector(SDValue Op, SelectionDAG &DAG,
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SDValue Vec = Op.getOperand(0);
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SDValue SubVec = Op.getOperand(1);
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SDValue Idx = Op.getOperand(2);
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if (!isa<ConstantSDNode>(Idx))
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return SDValue();
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unsigned IdxVal = Op.getConstantOperandVal(2);
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// Inserting undef is a nop. We can just return the original vector.
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if (SubVec.isUndef())
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return Vec;
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unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
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return Op;
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MVT OpVT = Op.getSimpleValueType();
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unsigned NumElems = OpVT.getVectorNumElements();
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SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
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// Extend to natively supported kshift.
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@ -5973,7 +5968,6 @@ static SDValue insert1BitVector(SDValue Op, SelectionDAG &DAG,
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MVT SubVecVT = SubVec.getSimpleValueType();
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unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
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assert(IdxVal + SubVecNumElems <= NumElems &&
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IdxVal % SubVecVT.getSizeInBits() == 0 &&
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"Unexpected index value in INSERT_SUBVECTOR");
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@ -6528,8 +6522,7 @@ static bool getTargetConstantBitsFromNode(SDValue Op, unsigned EltSizeInBits,
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}
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// Insert constant bits from a base and sub vector sources.
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if (Op.getOpcode() == ISD::INSERT_SUBVECTOR &&
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isa<ConstantSDNode>(Op.getOperand(2))) {
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if (Op.getOpcode() == ISD::INSERT_SUBVECTOR) {
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// TODO - support insert_subvector through bitcasts.
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if (EltSizeInBits != VT.getScalarSizeInBits())
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return false;
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@ -6551,8 +6544,7 @@ static bool getTargetConstantBitsFromNode(SDValue Op, unsigned EltSizeInBits,
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}
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// Extract constant bits from a subvector's source.
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if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
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isa<ConstantSDNode>(Op.getOperand(1))) {
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if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
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// TODO - support extract_subvector through bitcasts.
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if (EltSizeInBits != VT.getScalarSizeInBits())
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return false;
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@ -7227,15 +7219,11 @@ static bool getTargetShuffleAndZeroables(SDValue N, SmallVectorImpl<int> &Mask,
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SDValue Vec = V.getOperand(0);
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int NumVecElts = Vec.getValueType().getVectorNumElements();
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if (Vec.isUndef() && Size == NumVecElts) {
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auto *CIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
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int Idx = V.getConstantOperandVal(2);
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int NumSubElts = V.getOperand(1).getValueType().getVectorNumElements();
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if (CIdx && CIdx->getAPIntValue().ule(NumVecElts - NumSubElts)) {
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int Idx = CIdx->getZExtValue();
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if (M < Idx || (Idx + NumSubElts) <= M) {
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if (M < Idx || (Idx + NumSubElts) <= M)
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KnownUndef.setBit(i);
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}
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}
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}
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continue;
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}
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@ -7435,14 +7423,12 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
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SDValue Sub = N.getOperand(1);
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EVT SubVT = Sub.getValueType();
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unsigned NumSubElts = SubVT.getVectorNumElements();
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if (!isa<ConstantSDNode>(N.getOperand(2)) ||
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!N->isOnlyUserOf(Sub.getNode()))
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if (!N->isOnlyUserOf(Sub.getNode()))
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return false;
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uint64_t InsertIdx = N.getConstantOperandVal(2);
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// Handle INSERT_SUBVECTOR(SRC0, EXTRACT_SUBVECTOR(SRC1)).
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if (Sub.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
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Sub.getOperand(0).getValueType() == VT &&
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isa<ConstantSDNode>(Sub.getOperand(1))) {
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Sub.getOperand(0).getValueType() == VT) {
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uint64_t ExtractIdx = Sub.getConstantOperandVal(1);
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for (int i = 0; i != (int)NumElts; ++i)
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Mask.push_back(i);
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@ -7869,13 +7855,11 @@ static SDValue getShuffleScalarElt(SDValue Op, unsigned Index,
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}
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// Recurse into insert_subvector base/sub vector to find scalars.
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if (Opcode == ISD::INSERT_SUBVECTOR &&
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isa<ConstantSDNode>(Op.getOperand(2))) {
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if (Opcode == ISD::INSERT_SUBVECTOR) {
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SDValue Vec = Op.getOperand(0);
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SDValue Sub = Op.getOperand(1);
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EVT SubVT = Sub.getValueType();
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unsigned NumSubElts = SubVT.getVectorNumElements();
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uint64_t SubIdx = Op.getConstantOperandVal(2);
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unsigned NumSubElts = Sub.getValueType().getVectorNumElements();
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if (SubIdx <= Index && Index < (SubIdx + NumSubElts))
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return getShuffleScalarElt(Sub, Index - SubIdx, DAG, Depth + 1);
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@ -7892,8 +7876,7 @@ static SDValue getShuffleScalarElt(SDValue Op, unsigned Index,
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}
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// Recurse into extract_subvector src vector to find scalars.
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if (Opcode == ISD::EXTRACT_SUBVECTOR &&
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isa<ConstantSDNode>(Op.getOperand(1))) {
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if (Opcode == ISD::EXTRACT_SUBVECTOR) {
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SDValue Src = Op.getOperand(0);
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uint64_t SrcIdx = Op.getConstantOperandVal(1);
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return getShuffleScalarElt(Src, Index + SrcIdx, DAG, Depth + 1);
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@ -13175,8 +13158,7 @@ static SDValue lowerShuffleOfExtractsAsVperm(const SDLoc &DL, SDValue N0,
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SDValue WideVec = N0.getOperand(0);
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MVT WideVT = WideVec.getSimpleValueType();
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if (!WideVT.is256BitVector() || !isa<ConstantSDNode>(N0.getOperand(1)) ||
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!isa<ConstantSDNode>(N1.getOperand(1)))
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if (!WideVT.is256BitVector())
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return SDValue();
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// Match extracts of each half of the wide source vector. Commute the shuffle
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@ -13258,13 +13240,9 @@ static SDValue lowerShuffleAsBroadcast(const SDLoc &DL, MVT VT, SDValue V1,
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continue;
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}
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case ISD::EXTRACT_SUBVECTOR: {
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auto *ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(1));
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if (!ConstantIdx)
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break;
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// The extraction index adds to the existing offset.
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unsigned EltBitWidth = V.getScalarValueSizeInBits();
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unsigned Idx = ConstantIdx->getZExtValue();
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unsigned Idx = V.getConstantOperandVal(1);
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unsigned BeginOffset = Idx * EltBitWidth;
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BitOffset += BeginOffset;
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V = V.getOperand(0);
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@ -13272,12 +13250,8 @@ static SDValue lowerShuffleAsBroadcast(const SDLoc &DL, MVT VT, SDValue V1,
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}
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case ISD::INSERT_SUBVECTOR: {
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SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
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auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
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if (!ConstantIdx)
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break;
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int EltBitWidth = VOuter.getScalarValueSizeInBits();
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int Idx = (int)ConstantIdx->getZExtValue();
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int Idx = (int)V.getConstantOperandVal(2);
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int NumSubElts = (int)VInner.getSimpleValueType().getVectorNumElements();
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int BeginOffset = Idx * EltBitWidth;
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int EndOffset = BeginOffset + NumSubElts * EltBitWidth;
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@ -18529,12 +18503,8 @@ static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget,
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SDLoc dl(Op);
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SDValue Vec = Op.getOperand(0);
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SDValue Idx = Op.getOperand(1);
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uint64_t IdxVal = Op.getConstantOperandVal(1);
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if (!isa<ConstantSDNode>(Idx))
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return SDValue();
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unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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if (IdxVal == 0) // the operation is legal
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return Op;
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@ -34785,8 +34755,7 @@ static SDValue combineX86ShuffleChainWithExtract(
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unsigned &Offset = Offsets[i];
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Src = peekThroughBitcasts(Src);
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EVT BaseVT = Src.getValueType();
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while (Src.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
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isa<ConstantSDNode>(Src.getOperand(1))) {
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while (Src.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
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Offset += Src.getConstantOperandVal(1);
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Src = Src.getOperand(0);
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}
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@ -35886,9 +35855,7 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
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if (!(Imm == 0x31 &&
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Ins0.getOpcode() == ISD::INSERT_SUBVECTOR &&
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Ins1.getOpcode() == ISD::INSERT_SUBVECTOR &&
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Ins0.getValueType() == Ins1.getValueType() &&
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isa<ConstantSDNode>(Ins0.getOperand(2)) &&
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isa<ConstantSDNode>(Ins1.getOperand(2))))
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Ins0.getValueType() == Ins1.getValueType()))
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return SDValue();
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SDValue X = Ins0.getOperand(1);
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@ -47148,7 +47115,7 @@ static SDValue narrowExtractedVectorSelect(SDNode *Ext, SelectionDAG &DAG) {
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unsigned SelElts = SelVT.getVectorNumElements();
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unsigned CastedElts = WideVT.getVectorNumElements();
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unsigned ExtIdx = cast<ConstantSDNode>(Ext->getOperand(1))->getZExtValue();
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unsigned ExtIdx = Ext->getConstantOperandVal(1);
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if (SelElts % CastedElts == 0) {
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// The select has the same or more (narrower) elements than the extract
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// operand. The extraction index gets scaled by that factor.
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@ -47193,6 +47160,7 @@ static SDValue combineExtractSubvector(SDNode *N, SelectionDAG &DAG,
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MVT VT = N->getSimpleValueType(0);
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SDValue InVec = N->getOperand(0);
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unsigned IdxVal = N->getConstantOperandVal(1);
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SDValue InVecBC = peekThroughBitcasts(InVec);
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EVT InVecVT = InVec.getValueType();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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@ -47222,8 +47190,6 @@ static SDValue combineExtractSubvector(SDNode *N, SelectionDAG &DAG,
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if (SDValue V = narrowExtractedVectorSelect(N, DAG))
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return V;
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unsigned IdxVal = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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if (ISD::isBuildVectorAllZeros(InVec.getNode()))
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return getZeroVector(VT, Subtarget, DAG, SDLoc(N));
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