forked from OSchip/llvm-project
Also convert SUBREG_TO_REG to a KILL when relevant, like the other subreg
instructions. This does not affect codegen much because SUBREG_TO_REG is only used by X86 and X86 does not use the register scavenger, but it prevents verifier errors. llvm-svn: 106583
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@ -169,7 +169,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned InsReg = MI->getOperand(2).getReg();
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unsigned InsReg = MI->getOperand(2).getReg();
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unsigned InsSIdx = MI->getOperand(2).getSubReg();
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assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
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unsigned SubIdx = MI->getOperand(3).getImm();
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unsigned SubIdx = MI->getOperand(3).getImm();
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assert(SubIdx != 0 && "Invalid index for insert_subreg");
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assert(SubIdx != 0 && "Invalid index for insert_subreg");
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@ -182,13 +182,18 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
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DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
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DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
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if (DstSubReg == InsReg && InsSIdx == 0) {
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if (DstSubReg == InsReg) {
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// No need to insert an identify copy instruction.
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// No need to insert an identify copy instruction.
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// Watch out for case like this:
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// Watch out for case like this:
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// %RAX<def> = ...
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// %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
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// %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
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// We must leave %RAX live.
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// The first def is defining RAX, not EAX so the top bits were not
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if (DstReg != InsReg) {
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// zero extended.
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MI->setDesc(TII->get(TargetOpcode::KILL));
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MI->RemoveOperand(3); // SubIdx
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MI->RemoveOperand(1); // Imm
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DEBUG(dbgs() << "subreg: replace by: " << *MI);
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return true;
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}
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DEBUG(dbgs() << "subreg: eliminated!");
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DEBUG(dbgs() << "subreg: eliminated!");
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} else {
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} else {
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// Insert sub-register copy
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// Insert sub-register copy
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