forked from OSchip/llvm-project
Revert "[NFC] `IRBuilderBase::CreateAdd()`: place constant onto RHS"
Clang OpenMP codegen tests are failing,
will recommit afterwards.
This reverts commit 4723c9b3c6.
This commit is contained in:
Roman Lebedev
parent
42712698fd
commit
101aaf62ef
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@ -484,7 +484,7 @@ int test_mixed_sign_mull_overflow(int x, unsigned y) {
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// CHECK-NEXT: [[UnsignedOFlow:%.*]] = extractvalue { i32, i1 } %{{.*}}, 1
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// CHECK-NEXT: [[UnsignedResult:%.*]] = extractvalue { i32, i1 } %{{.*}}, 0
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// CHECK-NEXT: [[IsNegZext:%.*]] = zext i1 [[IsNeg]] to i32
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// CHECK-NEXT: [[MaxResult:%.*]] = add i32 [[IsNegZext]], 2147483647
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// CHECK-NEXT: [[MaxResult:%.*]] = add i32 2147483647, [[IsNegZext]]
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// CHECK-NEXT: [[SignedOFlow:%.*]] = icmp ugt i32 [[UnsignedResult]], [[MaxResult]]
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// CHECK-NEXT: [[OFlow:%.*]] = or i1 [[UnsignedOFlow]], [[SignedOFlow]]
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// CHECK-NEXT: [[NegativeResult:%.*]] = sub i32 0, [[UnsignedResult]]
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@ -523,7 +523,7 @@ int test_mixed_sign_mull_overflow_unsigned(int x, unsigned y) {
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int test_mixed_sign_mull_overflow_swapped(int x, unsigned y) {
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// CHECK: @test_mixed_sign_mull_overflow_swapped
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// CHECK: call { i32, i1 } @llvm.umul.with.overflow.i32
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// CHECK: add i32 [[Op0:%.*]], 2147483647
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// CHECK: add i32 2147483647
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int result;
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if (__builtin_mul_overflow(y, x, &result))
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return LongErrorCode;
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@ -533,7 +533,7 @@ int test_mixed_sign_mull_overflow_swapped(int x, unsigned y) {
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long long test_mixed_sign_mulll_overflow(long long x, unsigned long long y) {
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// CHECK: @test_mixed_sign_mulll_overflow
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// CHECK: call { i64, i1 } @llvm.umul.with.overflow.i64
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// CHECK: add i64 [[Op0:%.*]], 92233720368547
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// CHECK: add i64 92233720368547
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long long result;
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if (__builtin_mul_overflow(x, y, &result))
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return LongLongErrorCode;
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@ -543,7 +543,7 @@ long long test_mixed_sign_mulll_overflow(long long x, unsigned long long y) {
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long long test_mixed_sign_mulll_overflow_swapped(long long x, unsigned long long y) {
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// CHECK: @test_mixed_sign_mulll_overflow_swapped
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// CHECK: call { i64, i1 } @llvm.umul.with.overflow.i64
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// CHECK: add i64 [[Op0:%.*]], 92233720368547
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// CHECK: add i64 92233720368547
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long long result;
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if (__builtin_mul_overflow(y, x, &result))
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return LongLongErrorCode;
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@ -553,7 +553,7 @@ long long test_mixed_sign_mulll_overflow_swapped(long long x, unsigned long long
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long long test_mixed_sign_mulll_overflow_trunc_signed(long long x, unsigned long long y) {
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// CHECK: @test_mixed_sign_mulll_overflow_trunc_signed
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// CHECK: call { i64, i1 } @llvm.umul.with.overflow.i64
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// CHECK: add i64 [[Op0:%.*]], 2147483647
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// CHECK: add i64 2147483647
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// CHECK: trunc
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// CHECK: store
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int result;
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@ -1373,7 +1373,7 @@ vector double test_vec_vec_splatid(void) {
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vector signed int test_vec_vec_splati_ins_si(void) {
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// CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
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// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
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// CHECK-BE: [[T1:%.+]] = add i32 %{{.+}}, 2
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// CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
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// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
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// CHECK-BE: ret <4 x i32>
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// CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
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@ -1388,7 +1388,7 @@ vector signed int test_vec_vec_splati_ins_si(void) {
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vector unsigned int test_vec_vec_splati_ins_ui(void) {
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// CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
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// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
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// CHECK-BE: [[T1:%.+]] = add i32 %{{.+}}, 2
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// CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
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// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
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// CHECK-BE: ret <4 x i32>
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// CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
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@ -1403,7 +1403,7 @@ vector unsigned int test_vec_vec_splati_ins_ui(void) {
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vector float test_vec_vec_splati_ins_f(void) {
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// CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
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// CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
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// CHECK-BE: [[T1:%.+]] = add i32 %{{.+}}, 2
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// CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
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// CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
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// CHECK-BE: ret <4 x float>
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// CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
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@ -1415,13 +1415,13 @@ vector float test_vec_vec_splati_ins_f(void) {
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return vec_splati_ins(vfa, 0, 1.0f);
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}
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// In this test case, the second argument of vec_splati_ins is outside of the
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// expected range [0,1]. A mask of 0x01 is applied to obtain an in-range value
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// In this test case, the second argument of vec_splati_ins is outside of the
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// expected range [0,1]. A mask of 0x01 is applied to obtain an in-range value
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// for the second argument.
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vector signed int test_vec_vec_splati_ins_range(void) {
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// CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
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// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
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// CHECK-BE: [[T1:%.+]] = add i32 %{{.+}}, 2
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// CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
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// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
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// CHECK-BE: ret <4 x i32>
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// CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
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@ -170,7 +170,7 @@ char *nullptr_var(unsigned long offset) {
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_AGGREGATE:.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 1, i64 %[[OFFSET_RELOADED]]), !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_OVERFLOWED:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 1, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 0, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 %[[COMPUTED_OFFSET]], 0, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 0, %[[COMPUTED_OFFSET]], !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_GEP]], 0, !nosanitize
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// CHECK-SANITIZE-CPP-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = icmp eq i1 false, %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_DID_NOT_OVERFLOW:.*]] = xor i1 %[[COMPUTED_OFFSET_OVERFLOWED]], true, !nosanitize
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@ -256,7 +256,7 @@ char *one_var(unsigned long offset) {
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_AGGREGATE:.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 1, i64 %[[OFFSET_RELOADED]]), !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_OVERFLOWED:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 1, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 0, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 %[[COMPUTED_OFFSET]], 1, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 1, %[[COMPUTED_OFFSET]], !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_GEP]], 0, !nosanitize
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// CHECK-SANITIZE-C-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = and i1 %[[COMPUTED_GEP_IS_NOT_NULL]], icmp ne (i8* inttoptr (i64 1 to i8*), i8* null), !nosanitize
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// CHECK-SANITIZE-CPP-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = icmp eq i1 icmp ne (i8* inttoptr (i64 1 to i8*), i8* null), %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
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@ -342,7 +342,7 @@ char *allones_var(unsigned long offset) {
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_AGGREGATE:.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 1, i64 %[[OFFSET_RELOADED]]), !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_OVERFLOWED:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 1, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 0, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 %[[COMPUTED_OFFSET]], -1, !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 -1, %[[COMPUTED_OFFSET]], !nosanitize
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// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_GEP]], 0, !nosanitize
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// CHECK-SANITIZE-C-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = and i1 %[[COMPUTED_GEP_IS_NOT_NULL]], icmp ne (i8* inttoptr (i64 -1 to i8*), i8* null), !nosanitize
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// CHECK-SANITIZE-CPP-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = icmp eq i1 icmp ne (i8* inttoptr (i64 -1 to i8*), i8* null), %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
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@ -54,7 +54,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
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// CHECK-NEXT: %[[VAR9:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR8]]
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// CHECK-NEXT: %[[VAR10:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR9]] to i[[CHSIZE]]
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// CHECK-NEXT: store i[[CHSIZE]] %[[VAR10]], i[[CHSIZE]]* %[[SC1]], align [[CHALIGN]]
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uc1 = csc;
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// CHECK-NEXT: %[[VAR11:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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// CHECK-NEXT: %[[VAR12:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR11]]
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@ -98,7 +98,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
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// CHECK-NEXT: %[[VAR29:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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// CHECK-NEXT: %[[VAR30:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR29]]
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// CHECK-NEXT: store i[[LLSIZE]] %[[VAR30]], i[[LLSIZE]]* %[[SLL1]], align [[LLALIGN]]
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ull1 = csc;
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// CHECK-NEXT: %[[VAR31:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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// CHECK-NEXT: %[[VAR32:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR31]]
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@ -150,7 +150,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
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// CHECK-NEXT: %[[VAR54:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
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// CHECK-NEXT: store i[[CHSIZE]] %[[VAR52]], i[[CHSIZE]]* %[[VAR53]]
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// CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR54]]
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cuc1 = sc;
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// CHECK-NEXT: %[[VAR55:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]]
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// CHECK-NEXT: %[[VAR56:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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@ -251,7 +251,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
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// CHECK-NEXT: %[[VAR100:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR97]] to i[[ARSIZE]]
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// CHECK-NEXT: %[[VAR101:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR99]] to i[[ARSIZE]]
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// CHECK-NEXT: %[[VAR102:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR95]], %[[VAR100]]
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// CHECK-NEXT: %[[VAR103:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR101]], 0
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// CHECK-NEXT: %[[VAR103:[A-Za-z0-9.]+]] = add i[[ARSIZE]] 0, %[[VAR101]]
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// CHECK-NEXT: %[[VAR104:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR102]] to i[[CHSIZE]]
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// CHECK-NEXT: %[[VAR105:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR103]] to i[[CHSIZE]]
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// CHECK-NEXT: %[[VAR106:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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@ -269,7 +269,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
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// CHECK-NEXT: %[[VAR114:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR111]] to i[[ARSIZE]]
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// CHECK-NEXT: %[[VAR115:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR113]] to i[[ARSIZE]]
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// CHECK-NEXT: %[[VAR116:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR109]], %[[VAR114]]
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// CHECK-NEXT: %[[VAR117:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR115]], 0
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// CHECK-NEXT: %[[VAR117:[A-Za-z0-9.]+]] = add i[[ARSIZE]] 0, %[[VAR115]]
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// CHECK-NEXT: %[[VAR118:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR116]] to i[[CHSIZE]]
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// CHECK-NEXT: %[[VAR119:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR117]] to i[[CHSIZE]]
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// CHECK-NEXT: %[[VAR120:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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@ -285,7 +285,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
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// CHECK-NEXT: %[[VAR126:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
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// CHECK-NEXT: %[[VAR127:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR126]]
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// CHECK-NEXT: %[[VAR128:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR123]], %[[VAR125]]
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// CHECK-NEXT: %[[VAR129:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR127]], 0
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// CHECK-NEXT: %[[VAR129:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR127]]
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// CHECK-NEXT: %[[VAR130:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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// CHECK-NEXT: %[[VAR131:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
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// CHECK-NEXT: store i[[LLSIZE]] %[[VAR128]], i[[LLSIZE]]* %[[VAR130]]
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@ -299,12 +299,12 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
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// CHECK-NEXT: %[[VAR136:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
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// CHECK-NEXT: %[[VAR137:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR136]]
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// CHECK-NEXT: %[[VAR138:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR133]], %[[VAR135]]
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// CHECK-NEXT: %[[VAR139:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR137]], 0
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// CHECK-NEXT: %[[VAR139:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR137]]
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// CHECK-NEXT: %[[VAR140:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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// CHECK-NEXT: %[[VAR141:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
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// CHECK-NEXT: store i[[LLSIZE]] %[[VAR138]], i[[LLSIZE]]* %[[VAR140]]
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// CHECK-NEXT: store i[[LLSIZE]] %[[VAR139]], i[[LLSIZE]]* %[[VAR141]]
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csc1 = uc + csc;
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// CHECK-NEXT: %[[VAR142:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]]
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// CHECK-NEXT: %[[VAR143:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR142]] to i[[ARSIZE]]
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@ -315,7 +315,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
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// CHECK-NEXT: %[[VAR148:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR145]] to i[[ARSIZE]]
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// CHECK-NEXT: %[[VAR149:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR147]] to i[[ARSIZE]]
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// CHECK-NEXT: %[[VAR150:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR143]], %[[VAR148]]
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// CHECK-NEXT: %[[VAR151:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR149]], 0
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// CHECK-NEXT: %[[VAR151:[A-Za-z0-9.]+]] = add i[[ARSIZE]] 0, %[[VAR149]]
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// CHECK-NEXT: %[[VAR152:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR150]] to i[[CHSIZE]]
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// CHECK-NEXT: %[[VAR153:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR151]] to i[[CHSIZE]]
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// CHECK-NEXT: %[[VAR154:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
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@ -333,7 +333,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR162:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR159]] to i[[ARSIZE]]
|
||||
// CHECK-NEXT: %[[VAR163:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR161]] to i[[ARSIZE]]
|
||||
// CHECK-NEXT: %[[VAR164:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR157]], %[[VAR162]]
|
||||
// CHECK-NEXT: %[[VAR165:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR163]], 0
|
||||
// CHECK-NEXT: %[[VAR165:[A-Za-z0-9.]+]] = add i[[ARSIZE]] 0, %[[VAR163]]
|
||||
// CHECK-NEXT: %[[VAR166:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR164]] to i[[CHSIZE]]
|
||||
// CHECK-NEXT: %[[VAR167:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR165]] to i[[CHSIZE]]
|
||||
// CHECK-NEXT: %[[VAR168:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
|
|
@ -349,7 +349,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR174:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: %[[VAR175:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR174]]
|
||||
// CHECK-NEXT: %[[VAR176:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR171]], %[[VAR173]]
|
||||
// CHECK-NEXT: %[[VAR177:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR175]], 0
|
||||
// CHECK-NEXT: %[[VAR177:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR175]]
|
||||
// CHECK-NEXT: %[[VAR178:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR179:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR176]], i[[LLSIZE]]* %[[VAR178]]
|
||||
|
|
@ -363,7 +363,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR184:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: %[[VAR185:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR184]]
|
||||
// CHECK-NEXT: %[[VAR186:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR181]], %[[VAR183]]
|
||||
// CHECK-NEXT: %[[VAR187:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR185]], 0
|
||||
// CHECK-NEXT: %[[VAR187:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR185]]
|
||||
// CHECK-NEXT: %[[VAR188:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR189:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR186]], i[[LLSIZE]]* %[[VAR188]]
|
||||
|
|
@ -378,7 +378,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR195:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR192]] to i[[LLSIZE]]
|
||||
// CHECK-NEXT: %[[VAR196:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR194]] to i[[LLSIZE]]
|
||||
// CHECK-NEXT: %[[VAR197:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR190]], %[[VAR195]]
|
||||
// CHECK-NEXT: %[[VAR198:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR196]], 0
|
||||
// CHECK-NEXT: %[[VAR198:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR196]]
|
||||
// CHECK-NEXT: %[[VAR199:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR200:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR197]], i[[LLSIZE]]* %[[VAR199]]
|
||||
|
|
@ -393,7 +393,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR206:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR203]] to i[[LLSIZE]]
|
||||
// CHECK-NEXT: %[[VAR207:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR205]] to i[[LLSIZE]]
|
||||
// CHECK-NEXT: %[[VAR208:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR201]], %[[VAR206]]
|
||||
// CHECK-NEXT: %[[VAR209:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR207]], 0
|
||||
// CHECK-NEXT: %[[VAR209:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR207]]
|
||||
// CHECK-NEXT: %[[VAR210:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR211:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR208]], i[[LLSIZE]]* %[[VAR210]]
|
||||
|
|
@ -406,7 +406,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR215:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: %[[VAR216:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR215]]
|
||||
// CHECK-NEXT: %[[VAR217:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR212]], %[[VAR214]]
|
||||
// CHECK-NEXT: %[[VAR218:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR216]], 0
|
||||
// CHECK-NEXT: %[[VAR218:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR216]]
|
||||
// CHECK-NEXT: %[[VAR219:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR220:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR217]], i[[LLSIZE]]* %[[VAR219]]
|
||||
|
|
@ -419,12 +419,12 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR224:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: %[[VAR225:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR224]]
|
||||
// CHECK-NEXT: %[[VAR226:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR221]], %[[VAR223]]
|
||||
// CHECK-NEXT: %[[VAR227:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR225]], 0
|
||||
// CHECK-NEXT: %[[VAR227:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR225]]
|
||||
// CHECK-NEXT: %[[VAR228:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR229:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR226]], i[[LLSIZE]]* %[[VAR228]]
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR227]], i[[LLSIZE]]* %[[VAR229]]
|
||||
|
||||
|
||||
csll1 = ull + csc;
|
||||
// CHECK-NEXT: %[[VAR230:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]
|
||||
// CHECK-NEXT: %[[VAR231:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
|
|
@ -434,7 +434,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR235:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR232]] to i[[LLSIZE]]
|
||||
// CHECK-NEXT: %[[VAR236:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR234]] to i[[LLSIZE]]
|
||||
// CHECK-NEXT: %[[VAR237:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR230]], %[[VAR235]]
|
||||
// CHECK-NEXT: %[[VAR238:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR236]], 0
|
||||
// CHECK-NEXT: %[[VAR238:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR236]]
|
||||
// CHECK-NEXT: %[[VAR239:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR240:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR237]], i[[LLSIZE]]* %[[VAR239]]
|
||||
|
|
@ -449,7 +449,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR246:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR243]] to i[[LLSIZE]]
|
||||
// CHECK-NEXT: %[[VAR247:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR245]] to i[[LLSIZE]]
|
||||
// CHECK-NEXT: %[[VAR248:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR241]], %[[VAR246]]
|
||||
// CHECK-NEXT: %[[VAR249:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR247]], 0
|
||||
// CHECK-NEXT: %[[VAR249:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR247]]
|
||||
// CHECK-NEXT: %[[VAR250:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR251:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR248]], i[[LLSIZE]]* %[[VAR250]]
|
||||
|
|
@ -462,7 +462,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR255:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: %[[VAR256:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR255]]
|
||||
// CHECK-NEXT: %[[VAR257:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR252]], %[[VAR254]]
|
||||
// CHECK-NEXT: %[[VAR258:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR256]], 0
|
||||
// CHECK-NEXT: %[[VAR258:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR256]]
|
||||
// CHECK-NEXT: %[[VAR259:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR260:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR257]], i[[LLSIZE]]* %[[VAR259]]
|
||||
|
|
@ -475,7 +475,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR264:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: %[[VAR265:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR264]]
|
||||
// CHECK-NEXT: %[[VAR266:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR261]], %[[VAR263]]
|
||||
// CHECK-NEXT: %[[VAR267:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR265]], 0
|
||||
// CHECK-NEXT: %[[VAR267:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR265]]
|
||||
// CHECK-NEXT: %[[VAR268:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR269:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR266]], i[[LLSIZE]]* %[[VAR268]]
|
||||
|
|
@ -546,7 +546,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR319:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR316]], i[[LLSIZE]]* %[[VAR318]]
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR317]], i[[LLSIZE]]* %[[VAR319]]
|
||||
|
||||
|
||||
csc1 = cuc + sc;
|
||||
// CHECK-NEXT: %[[VAR320:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR321:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR320]]
|
||||
|
|
@ -666,7 +666,7 @@ void foo(signed char sc, unsigned char uc, signed long long sll,
|
|||
// CHECK-NEXT: %[[VAR405:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR402]], i[[LLSIZE]]* %[[VAR404]]
|
||||
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR403]], i[[LLSIZE]]* %[[VAR405]]
|
||||
|
||||
|
||||
csll1 = cull + sc;
|
||||
// CHECK-NEXT: %[[VAR406:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// CHECK-NEXT: %[[VAR407:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR406]]
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ int g(void) {return f(0);}
|
|||
// CHECK: call i32 @f
|
||||
int f(int b) {return 1+b;}
|
||||
// CHECK: load i32, i32* %{{.*}}
|
||||
// CHECK: add nsw i32 %{{.*}}, 1
|
||||
// CHECK: add nsw i32 1, %{{.*}}
|
||||
int h(void) {return f(1);}
|
||||
// CHECK: call i32 @f
|
||||
|
||||
|
|
|
|||
|
|
@ -909,9 +909,9 @@ void insert_int_idx_expr(ix9x3_t a, int i) {
|
|||
// CHECK-LABEL: @insert_int_idx_expr(
|
||||
// CHECK: [[I1:%.*]] = load i32, i32* %i.addr, align 4
|
||||
// CHECK-NEXT: [[I2:%.*]] = load i32, i32* %i.addr, align 4
|
||||
// CHECK-NEXT: [[I2_ADD:%.*]] = add nsw i32 [[I2]], 4
|
||||
// CHECK-NEXT: [[I2_ADD:%.*]] = add nsw i32 4, [[I2]]
|
||||
// CHECK-NEXT: [[ADD_EXT:%.*]] = sext i32 [[I2_ADD]] to i64
|
||||
// CHECK-NEXT: [[IDX2:%.*]] = add i64 [[ADD_EXT]], 18
|
||||
// CHECK-NEXT: [[IDX2:%.*]] = add i64 18, [[ADD_EXT]]
|
||||
// OPT-NEXT: [[CMP:%.*]] = icmp ult i64 [[IDX2]], 27
|
||||
// OPT-NEXT: call void @llvm.assume(i1 [[CMP]])
|
||||
// CHECK-NEXT: [[MAT:%.*]] = load <27 x i32>, <27 x i32>* [[MAT_ADDR:%.*]], align 4
|
||||
|
|
@ -1004,7 +1004,7 @@ double test_extract_matrix_pointer1(dx3x2_t **ptr, unsigned j) {
|
|||
// CHECK-LABEL: @test_extract_matrix_pointer1(
|
||||
// CHECK: [[J:%.*]] = load i32, i32* %j.addr, align 4
|
||||
// CHECK-NEXT: [[J_EXT:%.*]] = zext i32 [[J]] to i64
|
||||
// CHECK-NEXT: [[IDX:%.*]] = add i64 [[J_EXT]], 3
|
||||
// CHECK-NEXT: [[IDX:%.*]] = add i64 3, [[J_EXT]]
|
||||
// OPT-NEXT: [[CMP:%.*]] = icmp ult i64 [[IDX]], 6
|
||||
// OPT-NEXT: call void @llvm.assume(i1 [[CMP]])
|
||||
// CHECK-NEXT: [[PTR:%.*]] = load [6 x double]**, [6 x double]*** %ptr.addr, align 8
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ B::B() {
|
|||
// CHECK: %[[THIS_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8*
|
||||
// CHECK: %[[VBPTR:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 0
|
||||
// ...
|
||||
// CHECK: %[[VBASE_OFFSET:.*]] = add nsw i32 %{{.*}}, 0
|
||||
// CHECK: %[[VBASE_OFFSET:.*]] = add nsw i32 0, %{{.*}}
|
||||
// CHECK: %[[VTORDISP_VAL:.*]] = sub i32 %[[VBASE_OFFSET]], 8
|
||||
// CHECK: %[[THIS_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8*
|
||||
// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 %[[VBASE_OFFSET]]
|
||||
|
|
@ -74,7 +74,7 @@ B::~B() {
|
|||
// CHECK: %[[THIS_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8*
|
||||
// CHECK: %[[VBPTR:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 0
|
||||
// ...
|
||||
// CHECK: %[[VBASE_OFFSET:.*]] = add nsw i32 %{{.*}}, 0
|
||||
// CHECK: %[[VBASE_OFFSET:.*]] = add nsw i32 0, %{{.*}}
|
||||
// CHECK: %[[VTORDISP_VAL:.*]] = sub i32 %[[VBASE_OFFSET]], 8
|
||||
// CHECK: %[[THIS_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8*
|
||||
// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 %[[VBASE_OFFSET]]
|
||||
|
|
@ -138,7 +138,7 @@ void B::foo() {
|
|||
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]
|
||||
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1
|
||||
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 0, %[[VBOFFSET32]]
|
||||
// CHECK: %[[THIS8:.*]] = bitcast %struct.B* %[[THIS]] to i8*
|
||||
// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS8]], i32 %[[VBOFFSET]]
|
||||
// CHECK: %[[VBASE:.*]] = bitcast i8* %[[VBASE_i8]] to %struct.VBase*
|
||||
|
|
@ -162,7 +162,7 @@ void call_vbase_bar(B *obj) {
|
|||
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]
|
||||
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1
|
||||
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 0, %[[VBOFFSET32]]
|
||||
// CHECK: %[[VBASE:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET]]
|
||||
//
|
||||
// CHECK: %[[OBJ_i8:.*]] = bitcast %struct.B* %[[OBJ]] to i8*
|
||||
|
|
@ -171,7 +171,7 @@ void call_vbase_bar(B *obj) {
|
|||
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]
|
||||
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1
|
||||
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 0, %[[VBOFFSET32]]
|
||||
// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET]]
|
||||
// CHECK: %[[VFPTR:.*]] = bitcast i8* %[[VBASE_i8]] to void (i8*)***
|
||||
// CHECK: %[[VFTABLE:.*]] = load void (i8*)**, void (i8*)*** %[[VFPTR]]
|
||||
|
|
@ -194,7 +194,7 @@ void delete_B(B *obj) {
|
|||
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]
|
||||
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1
|
||||
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 0, %[[VBOFFSET32]]
|
||||
// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET]]
|
||||
// CHECK: %[[VBASE:.*]] = bitcast i8* %[[VBASE_i8]] to %struct.B*
|
||||
//
|
||||
|
|
@ -204,7 +204,7 @@ void delete_B(B *obj) {
|
|||
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]
|
||||
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1
|
||||
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0
|
||||
// CHECK: %[[VBOFFSET:.*]] = add nsw i32 0, %[[VBOFFSET32]]
|
||||
// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET]]
|
||||
// CHECK: %[[VFPTR:.*]] = bitcast i8* %[[VBASE_i8]] to i8* (%struct.B*, i32)***
|
||||
// CHECK: %[[VFTABLE:.*]] = load i8* (%struct.B*, i32)**, i8* (%struct.B*, i32)*** %[[VFPTR]]
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ A* a() { return x; }
|
|||
// MSVC: %[[vbtable:.*]] = load i32*, i32** %[[vbptr]]
|
||||
// MSVC: %[[entry:.*]] = getelementptr inbounds i32, i32* {{.*}}, i32 1
|
||||
// MSVC: %[[offset:.*]] = load i32, i32* %[[entry]]
|
||||
// MSVC: add nsw i32 %[[offset]], 0
|
||||
// MSVC: add nsw i32 0, %[[offset]]
|
||||
// MSVC: }
|
||||
|
||||
B* b() { return x; }
|
||||
|
|
@ -41,7 +41,7 @@ B* b() { return x; }
|
|||
// MSVC: %[[vbtable:.*]] = load i32*, i32** %[[vbptr]]
|
||||
// MSVC: %[[entry:.*]] = getelementptr inbounds i32, i32* {{.*}}, i32 2
|
||||
// MSVC: %[[offset:.*]] = load i32, i32* %[[entry]]
|
||||
// MSVC: add nsw i32 %[[offset]], 0
|
||||
// MSVC: add nsw i32 0, %[[offset]]
|
||||
// MSVC: }
|
||||
|
||||
|
||||
|
|
@ -60,7 +60,7 @@ BB* c() { return x; }
|
|||
// MSVC: %[[vbtable:.*]] = load i32*, i32** %[[vbptr]]
|
||||
// MSVC: %[[entry:.*]] = getelementptr inbounds i32, i32* {{.*}}, i32 4
|
||||
// MSVC: %[[offset:.*]] = load i32, i32* %[[entry]]
|
||||
// MSVC: add nsw i32 %[[offset]], 0
|
||||
// MSVC: add nsw i32 0, %[[offset]]
|
||||
// MSVC: }
|
||||
|
||||
// Put the vbptr at a non-zero offset inside a non-virtual base.
|
||||
|
|
@ -79,7 +79,7 @@ BB* d() { return y; }
|
|||
// MSVC: %[[vbtable:.*]] = load i32*, i32** %[[vbptr]]
|
||||
// MSVC: %[[entry:.*]] = getelementptr inbounds i32, i32* {{.*}}, i32 4
|
||||
// MSVC: %[[offset:.*]] = load i32, i32* %[[entry]]
|
||||
// MSVC: add nsw i32 %[[offset]], 4
|
||||
// MSVC: add nsw i32 4, %[[offset]]
|
||||
// MSVC: }
|
||||
|
||||
// CHECK: attributes [[NUW]] = { mustprogress noinline nounwind{{.*}} }
|
||||
|
|
|
|||
|
|
@ -1211,8 +1211,6 @@ private:
|
|||
public:
|
||||
Value *CreateAdd(Value *LHS, Value *RHS, const Twine &Name = "",
|
||||
bool HasNUW = false, bool HasNSW = false) {
|
||||
if (!isa<Constant>(RHS) && isa<Constant>(LHS))
|
||||
std::swap(LHS, RHS);
|
||||
if (auto *LC = dyn_cast<Constant>(LHS))
|
||||
if (auto *RC = dyn_cast<Constant>(RHS))
|
||||
return Insert(Folder.CreateAdd(LC, RC, HasNUW, HasNSW), Name);
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ target triple = "x86_64-unknown-linux-gnu"
|
|||
; CHECK-NEXT: store i64 %1, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc_foo, i64 0, i64 0)
|
||||
; RELOC-LABEL: define void @foo
|
||||
; RELOC-NEXT: %1 = load i64, i64* @__llvm_profile_counter_bias
|
||||
; RELOC-NEXT: %2 = add i64 %1, ptrtoint ([1 x i64]* @__profc_foo to i64)
|
||||
; RELOC-NEXT: %2 = add i64 ptrtoint ([1 x i64]* @__profc_foo to i64), %1
|
||||
; RELOC-NEXT: %3 = inttoptr i64 %2 to i64*
|
||||
; RELOC-NEXT: %pgocount = load i64, i64* %3
|
||||
; RELOC-NEXT: %4 = add i64 %pgocount, 1
|
||||
|
|
|
|||
|
|
@ -22,20 +22,20 @@ define i32 @foo(i32 %guard, ...) {
|
|||
|
||||
; CHECK-LABEL: @foo
|
||||
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
|
||||
; CHECK: [[B:%.*]] = add i64 [[A]], 192
|
||||
; CHECK: [[B:%.*]] = add i64 192, [[A]]
|
||||
; CHECK: alloca {{.*}} [[B]]
|
||||
|
||||
; We expect three memcpy operations: one for the general purpose registers,
|
||||
; one for floating-point/SIMD ones, and one for thre remaining arguments.
|
||||
|
||||
; Propagate the GR shadow values on for the va_list::__gp_top, adjust the
|
||||
; Propagate the GR shadow values on for the va_list::__gp_top, adjust the
|
||||
; offset in the __msan_va_arg_tls based on va_list:__gp_off, and finally
|
||||
; issue the memcpy.
|
||||
; CHECK: [[GRP:%.*]] = getelementptr inbounds i8, i8* {{%.*}}, i64 {{%.*}}
|
||||
; CHECK: [[GRSIZE:%.*]] = sub i64 64, {{%.*}}
|
||||
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 {{%.*}}, i8* align 8 [[GRP]], i64 [[GRSIZE]], i1 false)
|
||||
|
||||
; Propagate the VR shadow values on for the va_list::__vr_top, adjust the
|
||||
; Propagate the VR shadow values on for the va_list::__vr_top, adjust the
|
||||
; offset in the __msan_va_arg_tls based on va_list:__vr_off, and finally
|
||||
; issue the memcpy.
|
||||
; CHECK: [[VRP:%.*]] = getelementptr inbounds i8, i8* {{%.*}}, i64 {{%.*}}
|
||||
|
|
@ -53,7 +53,7 @@ declare void @llvm.va_end(i8*) #2
|
|||
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
|
||||
|
||||
define i32 @bar() {
|
||||
%1 = call i32 (i32, ...) @foo(i32 0, i32 1, i32 2, double 3.000000e+00,
|
||||
%1 = call i32 (i32, ...) @foo(i32 0, i32 1, i32 2, double 3.000000e+00,
|
||||
double 4.000000e+00, i32 5, i32 6,
|
||||
double 7.000000e+00, i32 8, i32 9, i32 10, i32 11)
|
||||
ret i32 %1
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ define i32 @foo(i32 %guard, ...) {
|
|||
|
||||
; CHECK-LABEL: @foo
|
||||
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
|
||||
; CHECK: [[B:%.*]] = add i64 [[A]], 0
|
||||
; CHECK: [[B:%.*]] = add i64 0, [[A]]
|
||||
; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
|
||||
|
||||
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ define i32 @foo(i32 %guard, ...) {
|
|||
|
||||
; CHECK-LABEL: @foo
|
||||
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
|
||||
; CHECK: [[B:%.*]] = add i64 [[A]], 0
|
||||
; CHECK: [[B:%.*]] = add i64 0, [[A]]
|
||||
; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
|
||||
|
||||
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ define i32 @foo(i32 %guard, ...) {
|
|||
|
||||
; CHECK-LABEL: @foo
|
||||
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
|
||||
; CHECK: [[B:%.*]] = add i64 [[A]], 0
|
||||
; CHECK: [[B:%.*]] = add i64 0, [[A]]
|
||||
; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
|
||||
|
||||
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ define i32 @foo(i32 %guard, ...) {
|
|||
|
||||
; CHECK-LABEL: @foo
|
||||
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
|
||||
; CHECK: [[B:%.*]] = add i64 [[A]], 0
|
||||
; CHECK: [[B:%.*]] = add i64 0, [[A]]
|
||||
; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
|
||||
|
||||
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false)
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ define i64 @foo(i64 %guard, ...) {
|
|||
|
||||
; CHECK-LABEL: @foo
|
||||
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
|
||||
; CHECK: [[B:%.*]] = add i64 [[A]], 160
|
||||
; CHECK: [[B:%.*]] = add i64 160, [[A]]
|
||||
; CHECK: alloca {{.*}} [[B]]
|
||||
|
||||
; We expect two memcpy operations: one for the register save area, and one for
|
||||
|
|
|
|||
|
|
@ -350,7 +350,7 @@ attributes #0 = { "target-features"="+fxsr,+x87,-sse" }
|
|||
|
||||
; CHECK: [[OSIZE:%[0-9]+]] = load i64, i64* [[VA_ARG_OVERFLOW_SIZE]]
|
||||
; Register save area is 48 bytes for non-SSE builds.
|
||||
; CHECK: [[SIZE:%[0-9]+]] = add i64 [[OSIZE]], 48
|
||||
; CHECK: [[SIZE:%[0-9]+]] = add i64 48, [[OSIZE]]
|
||||
; CHECK: [[SHADOWS:%[0-9]+]] = alloca i8, i64 [[SIZE]]
|
||||
; CHECK: [[VA_ARG_SHADOW]]
|
||||
; CHECK: call void @llvm.memcpy{{.*}}(i8* align 8 [[SHADOWS]], {{.*}}, i64 [[SIZE]]
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ define void @f(i32* noalias %a, i32* noalias %b, i32* noalias %c, i32* noalias %
|
|||
; CHECK-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
|
||||
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
|
||||
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[MUL_RESULT]], 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i32 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP2]], 0
|
||||
|
|
@ -163,7 +163,7 @@ define void @f_with_offset(i32* noalias %b, i32* noalias %c, i32* noalias %d, i3
|
|||
; CHECK-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
|
||||
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
|
||||
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[MUL_RESULT]], 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i32 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP2]], 0
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@ define void @fadd_strict_interleave(float* noalias nocapture readonly %a, float*
|
|||
; CHECK-ORDERED: %[[STEPVEC1:.*]] = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
|
||||
; CHECK-ORDERED: %[[STEPVEC_ADD1:.*]] = add <vscale x 4 x i64> %[[STEPVEC1]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 0, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
|
||||
; CHECK-ORDERED: %[[STEPVEC_MUL:.*]] = mul <vscale x 4 x i64> %[[STEPVEC_ADD1]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 2, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
|
||||
; CHECK-ORDERED: %[[INDUCTION:.*]] = add <vscale x 4 x i64> %[[STEPVEC_MUL]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 0, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
|
||||
; CHECK-ORDERED: %[[INDUCTION:.*]] = add <vscale x 4 x i64> shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 0, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer), %[[STEPVEC_MUL]]
|
||||
; CHECK-ORDERED: vector.body
|
||||
; CHECK-ORDERED: %[[VEC_PHI2:.*]] = phi float [ %[[LOAD2]], %vector.ph ], [ %[[RDX2:.*]], %vector.body ]
|
||||
; CHECK-ORDERED: %[[VEC_PHI1:.*]] = phi float [ %[[LOAD1]], %vector.ph ], [ %[[RDX1:.*]], %vector.body ]
|
||||
|
|
@ -149,7 +149,7 @@ define void @fadd_strict_interleave(float* noalias nocapture readonly %a, float*
|
|||
; CHECK-UNORDERED: %[[STEPVEC1:.*]] = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
|
||||
; CHECK-UNORDERED: %[[STEPVEC_ADD1:.*]] = add <vscale x 4 x i64> %[[STEPVEC1]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 0, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
|
||||
; CHECK-UNORDERED: %[[STEPVEC_MUL:.*]] = mul <vscale x 4 x i64> %[[STEPVEC_ADD1]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 2, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
|
||||
; CHECK-UNORDERED: %[[INDUCTION:.*]] = add <vscale x 4 x i64> %[[STEPVEC_MUL]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 0, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
|
||||
; CHECK-UNORDERED: %[[INDUCTION:.*]] = add <vscale x 4 x i64> shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 0, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer), %[[STEPVEC_MUL]]
|
||||
; CHECK-UNORDERED: vector.body
|
||||
; CHECK-UNORDERED: %[[VEC_PHI2:.*]] = phi <vscale x 4 x float> [ %[[INS_ELT2]], %vector.ph ], [ %[[VEC_FADD2:.*]], %vector.body ]
|
||||
; CHECK-UNORDERED: %[[VEC_PHI1:.*]] = phi <vscale x 4 x float> [ %[[INS_ELT1]], %vector.ph ], [ %[[VEC_FADD1:.*]], %vector.body ]
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ define void @pointer_induction_used_as_vector(i8** noalias %start.1, i8* noalias
|
|||
; CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
|
||||
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[INDEX]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 2 x i64> [[TMP6]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 0, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 0, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer), [[TMP6]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 2 x i64> [[DOTSPLAT]], [[TMP7]]
|
||||
; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, i8* [[START_2]], <vscale x 2 x i64> [[TMP8]]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 0
|
||||
|
|
@ -126,7 +126,7 @@ define void @pointer_induction(i8* noalias %start, i64 %N) {
|
|||
; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
|
||||
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[INDEX1]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 2 x i64> [[TMP5]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 0, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 0, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer), [[TMP5]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 2 x i64> [[DOTSPLAT]], [[TMP6]]
|
||||
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[START]], <vscale x 2 x i64> [[TMP7]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX1]], 0
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ define void @test_stride-1_4i32(i32* readonly %data, i32* noalias nocapture %dst
|
|||
; CHECK-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 [[TMP0]])
|
||||
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
|
||||
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[MUL_RESULT]], 2
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 2, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = sub i32 2, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 2
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP1]], 2
|
||||
|
|
@ -431,7 +431,7 @@ define void @test_stride_noninvar_4i32(i32* readonly %data, i32* noalias nocaptu
|
|||
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
|
||||
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[N_VEC]], 8
|
||||
; CHECK-NEXT: [[IND_END:%.*]] = add i32 [[TMP0]], 3
|
||||
; CHECK-NEXT: [[IND_END:%.*]] = add i32 3, [[TMP0]]
|
||||
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
|
||||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
|
|
@ -549,11 +549,11 @@ define void @test_stride_noninvar3_4i32(i32* readonly %data, i32* noalias nocapt
|
|||
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
|
||||
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[N_VEC]], [[X:%.*]]
|
||||
; CHECK-NEXT: [[IND_END:%.*]] = add i32 [[TMP0]], 3
|
||||
; CHECK-NEXT: [[IND_END:%.*]] = add i32 3, [[TMP0]]
|
||||
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP1]], <i32 3, i32 3, i32 3, i32 3>
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> <i32 3, i32 3, i32 3, i32 3>, [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[X]], 4
|
||||
; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT2]], <4 x i32> poison, <4 x i32> zeroinitializer
|
||||
|
|
|
|||
|
|
@ -17,13 +17,13 @@ define i32 @conversion_cost1(i32 %n, i8* nocapture %A, float* nocapture %B) noun
|
|||
; CHECK: vector.ph:
|
||||
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP4]], 32
|
||||
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP4]], [[N_MOD_VF]]
|
||||
; CHECK-NEXT: [[IND_END:%.*]] = add i64 [[N_VEC]], 3
|
||||
; CHECK-NEXT: [[IND_END:%.*]] = add i64 3, [[N_VEC]]
|
||||
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
|
||||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <32 x i64> [ <i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15, i64 16, i64 17, i64 18, i64 19, i64 20, i64 21, i64 22, i64 23, i64 24, i64 25, i64 26, i64 27, i64 28, i64 29, i64 30, i64 31, i64 32, i64 33, i64 34>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <32 x i8> [ <i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], 3
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 3, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 1
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 2
|
||||
|
|
@ -115,7 +115,7 @@ define i32 @conversion_cost2(i32 %n, i8* nocapture %A, float* nocapture %B) noun
|
|||
; CHECK: vector.ph:
|
||||
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP4]], 8
|
||||
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP4]], [[N_MOD_VF]]
|
||||
; CHECK-NEXT: [[IND_END:%.*]] = add i64 [[N_VEC]], 9
|
||||
; CHECK-NEXT: [[IND_END:%.*]] = add i64 9, [[N_VEC]]
|
||||
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
|
||||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
|
|
@ -123,7 +123,7 @@ define i32 @conversion_cost2(i32 %n, i8* nocapture %A, float* nocapture %B) noun
|
|||
; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
|
||||
; CHECK-NEXT: [[STEP_ADD1:%.*]] = add <2 x i64> [[STEP_ADD]], <i64 2, i64 2>
|
||||
; CHECK-NEXT: [[STEP_ADD2:%.*]] = add <2 x i64> [[STEP_ADD1]], <i64 2, i64 2>
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], 9
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 9, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 1
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 2
|
||||
|
|
|
|||
|
|
@ -1026,7 +1026,7 @@ define i32 @test_non_zero_start(i64 %len, i1* %test_base) {
|
|||
; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP81:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP82:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP83:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], 1024
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1024, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 1
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 2
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ define void @foo() {
|
|||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 2, i64 3, i64 4, i64 5>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 2, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 1
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 2
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ define void @can_sink_after_store(i32 %x, i32* %ptr, i64 %tc) local_unnamed_addr
|
|||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i32> [ [[VECTOR_RECUR_INIT]], [[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [257 x i32], [257 x i32]* @p, i64 0, i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 0
|
||||
|
|
@ -107,7 +107,7 @@ define void @sink_sdiv(i32 %x, i32* %ptr, i64 %tc) local_unnamed_addr #0 {
|
|||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i32> [ [[VECTOR_RECUR_INIT]], [[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [257 x i32], [257 x i32]* @p, i64 0, i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 0
|
||||
|
|
@ -190,7 +190,7 @@ define void @can_sink_with_additional_user(i32 %x, i32* %ptr, i64 %tc) {
|
|||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i32> [ [[VECTOR_RECUR_INIT]], [[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [257 x i32], [257 x i32]* @p, i64 0, i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 0
|
||||
|
|
@ -645,7 +645,7 @@ define void @sink_dominance(i32* %ptr, i32 %N) {
|
|||
; CHECK: vector.scevcheck:
|
||||
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 1)
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[UMAX]], -1
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 0, [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP1]], 0
|
||||
|
|
@ -732,7 +732,7 @@ define void @sink_dominance_2(i32* %ptr, i32 %N) {
|
|||
; CHECK: vector.scevcheck:
|
||||
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 1)
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[UMAX]], -1
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 0, [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP1]], 0
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ define float @minloopattr(float* nocapture readonly %arg) #0 {
|
|||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ [[MINMAX_IDENT_SPLAT]], [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, float* [[ARG]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, float* [[TMP1]], i32 0
|
||||
|
|
@ -66,7 +66,7 @@ define float @minloopattr(float* nocapture readonly %arg) #0 {
|
|||
; CHECK-NEXT: [[TMP5]] = select <4 x i1> [[TMP4]], <4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]]
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
|
||||
; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
|
||||
; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
|
||||
; CHECK: middle.block:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[TMP5]])
|
||||
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 65536, 65536
|
||||
|
|
@ -84,7 +84,7 @@ define float @minloopattr(float* nocapture readonly %arg) #0 {
|
|||
; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
|
||||
; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
|
||||
; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537
|
||||
; CHECK-NEXT: br i1 [[T8]], label [[OUT]], label [[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]
|
||||
; CHECK-NEXT: br i1 [[T8]], label [[OUT]], label [[LOOP]], [[LOOP2:!llvm.loop !.*]]
|
||||
; CHECK: out:
|
||||
; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ]
|
||||
; CHECK-NEXT: ret float [[T6_LCSSA]]
|
||||
|
|
|
|||
|
|
@ -206,13 +206,13 @@ define void @bug18724(i1 %cond) {
|
|||
; UNROLL: vector.ph:
|
||||
; UNROLL-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2
|
||||
; UNROLL-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
|
||||
; UNROLL-NEXT: [[IND_END:%.*]] = add i64 [[N_VEC]], undef
|
||||
; UNROLL-NEXT: [[IND_END:%.*]] = add i64 undef, [[N_VEC]]
|
||||
; UNROLL-NEXT: br label [[VECTOR_BODY:%.*]]
|
||||
; UNROLL: vector.body:
|
||||
; UNROLL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ]
|
||||
; UNROLL-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[PRED_STORE_CONTINUE4]] ]
|
||||
; UNROLL-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[PREDPHI5:%.*]], [[PRED_STORE_CONTINUE4]] ]
|
||||
; UNROLL-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], undef
|
||||
; UNROLL-NEXT: [[OFFSET_IDX:%.*]] = add i64 undef, [[INDEX]]
|
||||
; UNROLL-NEXT: [[INDUCTION:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; UNROLL-NEXT: [[INDUCTION1:%.*]] = add i64 [[OFFSET_IDX]], 1
|
||||
; UNROLL-NEXT: [[TMP4:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDUCTION]]
|
||||
|
|
@ -274,13 +274,13 @@ define void @bug18724(i1 %cond) {
|
|||
; UNROLL-NOSIMPLIFY: vector.ph:
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 2
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[IND_END:%.*]] = add i64 [[N_VEC]], undef
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[IND_END:%.*]] = add i64 undef, [[N_VEC]]
|
||||
; UNROLL-NOSIMPLIFY-NEXT: br label [[VECTOR_BODY:%.*]]
|
||||
; UNROLL-NOSIMPLIFY: vector.body:
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ]
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[PRED_STORE_CONTINUE4]] ]
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[PREDPHI5:%.*]], [[PRED_STORE_CONTINUE4]] ]
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], undef
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[OFFSET_IDX:%.*]] = add i64 undef, [[INDEX]]
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION1:%.*]] = add i64 [[OFFSET_IDX]], 1
|
||||
; UNROLL-NOSIMPLIFY-NEXT: [[TMP3:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDUCTION]]
|
||||
|
|
@ -348,12 +348,12 @@ define void @bug18724(i1 %cond) {
|
|||
; VEC: vector.ph:
|
||||
; VEC-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2
|
||||
; VEC-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
|
||||
; VEC-NEXT: [[IND_END:%.*]] = add i64 [[N_VEC]], undef
|
||||
; VEC-NEXT: [[IND_END:%.*]] = add i64 undef, [[N_VEC]]
|
||||
; VEC-NEXT: br label [[VECTOR_BODY:%.*]]
|
||||
; VEC: vector.body:
|
||||
; VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ]
|
||||
; VEC-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ <i32 undef, i32 0>, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[PRED_STORE_CONTINUE2]] ]
|
||||
; VEC-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], undef
|
||||
; VEC-NEXT: [[OFFSET_IDX:%.*]] = add i64 undef, [[INDEX]]
|
||||
; VEC-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; VEC-NEXT: [[TMP5:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[TMP4]]
|
||||
; VEC-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i32 0
|
||||
|
|
|
|||
|
|
@ -164,7 +164,7 @@ for.end6: ; preds = %for.end6.loopexit,
|
|||
; CHECK-NEXT: [[DOTSPLATINSERT5:%.*]] = insertelement <8 x i32> poison, i32 [[TMP3]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT6:%.*]] = shufflevector <8 x i32> [[DOTSPLATINSERT5]], <8 x i32> poison, <8 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = mul <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[DOTSPLAT6]]
|
||||
; CHECK-NEXT: [[INDUCTION7:%.*]] = add <8 x i32> [[TMP4]], zeroinitializer
|
||||
; CHECK-NEXT: [[INDUCTION7:%.*]] = add <8 x i32> zeroinitializer, [[TMP4]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP3]], 8
|
||||
; CHECK-NEXT: [[DOTSPLATINSERT8:%.*]] = insertelement <8 x i32> poison, i32 [[TMP5]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT9:%.*]] = shufflevector <8 x i32> [[DOTSPLATINSERT8]], <8 x i32> poison, <8 x i32> zeroinitializer
|
||||
|
|
|
|||
|
|
@ -813,7 +813,7 @@ for.end:
|
|||
; CHECK-LABEL: @PR32419(
|
||||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %[[PRED_UREM_CONTINUE4:.*]] ]
|
||||
; CHECK: [[OFFSET_IDX:%.*]] = add i32 [[INDEX]], -20
|
||||
; CHECK: [[OFFSET_IDX:%.*]] = add i32 -20, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[OFFSET_IDX]] to i16
|
||||
; CHECK: [[TMP8:%.*]] = add i16 [[TMP1]], 0
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = urem i16 %b, [[TMP8]]
|
||||
|
|
@ -851,8 +851,8 @@ for.end:
|
|||
}
|
||||
|
||||
; Ensure that the shuffle vector for first order recurrence is inserted
|
||||
; correctly after all the phis. These new phis correspond to new IVs
|
||||
; that are generated by optimizing non-free truncs of IVs to IVs themselves
|
||||
; correctly after all the phis. These new phis correspond to new IVs
|
||||
; that are generated by optimizing non-free truncs of IVs to IVs themselves
|
||||
define i64 @trunc_with_first_order_recurrence() {
|
||||
; CHECK-LABEL: trunc_with_first_order_recurrence
|
||||
; CHECK-LABEL: vector.body:
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ define void @doit1(i32 %n, i32 %step) local_unnamed_addr {
|
|||
; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP4]], i8 [[TMP5]])
|
||||
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
|
||||
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i8 [[MUL_RESULT]], 0
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i8 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = sub i8 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i8 [[TMP7]], 0
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = icmp slt i8 [[TMP6]], 0
|
||||
|
|
@ -73,7 +73,7 @@ define void @doit1(i32 %n, i32 %step) local_unnamed_addr {
|
|||
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[STEP]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP18]], zeroinitializer
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> zeroinitializer, [[TMP18]]
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[STEP]], 4
|
||||
; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP19]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT2]], <4 x i32> poison, <4 x i32> zeroinitializer
|
||||
|
|
@ -177,7 +177,7 @@ define void @doit2(i32 %n, i32 %step) local_unnamed_addr {
|
|||
; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP4]], i8 [[TMP5]])
|
||||
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
|
||||
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i8 [[MUL_RESULT]], 0
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i8 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = sub i8 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i8 [[TMP7]], 0
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i8 [[TMP6]], 0
|
||||
|
|
@ -199,7 +199,7 @@ define void @doit2(i32 %n, i32 %step) local_unnamed_addr {
|
|||
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[STEP]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP18]], zeroinitializer
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> zeroinitializer, [[TMP18]]
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[STEP]], 4
|
||||
; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP19]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT2]], <4 x i32> poison, <4 x i32> zeroinitializer
|
||||
|
|
@ -377,7 +377,7 @@ define void @doit4(i32 %n, i8 signext %cstep) local_unnamed_addr {
|
|||
; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP3]], i8 [[TMP4]])
|
||||
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
|
||||
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = add i8 [[MUL_RESULT]], 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = add i8 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i8 [[TMP6]], 0
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i8 [[TMP5]], 0
|
||||
|
|
@ -396,7 +396,7 @@ define void @doit4(i32 %n, i8 signext %cstep) local_unnamed_addr {
|
|||
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[CONV]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP15]], zeroinitializer
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> zeroinitializer, [[TMP15]]
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[CONV]], 4
|
||||
; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP16]], i32 0
|
||||
; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT2]], <4 x i32> poison, <4 x i32> zeroinitializer
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ define i16 @test_true_and_false_branch_equal() {
|
|||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SREM_CONTINUE4:%.*]] ]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[INDEX]] to i16
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 [[TMP0]], 99
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 99, [[TMP0]]
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[OFFSET_IDX]], i32 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <2 x i16> [[BROADCAST_SPLAT]], <i16 0, i16 1>
|
||||
|
|
@ -51,7 +51,7 @@ define i16 @test_true_and_false_branch_equal() {
|
|||
; CHECK-NEXT: store i16 [[TMP15]], i16* @v_39, align 1
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12
|
||||
; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
|
||||
; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
|
||||
; CHECK: middle.block:
|
||||
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 12, 12
|
||||
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
|
||||
|
|
@ -74,7 +74,7 @@ define i16 @test_true_and_false_branch_equal() {
|
|||
; CHECK-NEXT: store i16 [[COND6]], i16* @v_39, align 1
|
||||
; CHECK-NEXT: [[INC7]] = add nsw i16 [[I_07]], 1
|
||||
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[INC7]], 111
|
||||
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT]], !llvm.loop [[LOOP2:![0-9]+]]
|
||||
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT]], [[LOOP2:!llvm.loop !.*]]
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: [[RV:%.*]] = load i16, i16* @v_39, align 1
|
||||
; CHECK-NEXT: ret i16 [[RV]]
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ define i8 @widget(i8* %arr, i8 %t9) {
|
|||
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[T1_0_LCSSA1]], -1
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[TMP3]], [[ARR2]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i8 [[TMP5]], 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i8 1, [[TMP5]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = sub i8 1, [[TMP5]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i8 [[TMP7]], 1
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = icmp slt i8 [[TMP6]], 1
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ define void @load_clamped_index(i32* %A, i32* %B, i32 %N) {
|
|||
; CHECK: vector.scevcheck:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i2
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i2 [[TMP1]], 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i2 0, [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = sub i2 0, [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i2 [[TMP3]], 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i2 [[TMP2]], 0
|
||||
|
|
@ -109,7 +109,7 @@ define void @store_clamped_index(i32* %A, i32* %B, i32 %N) {
|
|||
; CHECK: vector.scevcheck:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i2
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i2 [[TMP1]], 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i2 0, [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = sub i2 0, [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i2 [[TMP3]], 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i2 [[TMP2]], 0
|
||||
|
|
@ -277,7 +277,7 @@ define void @clamped_index_equal_dependence(i32* %A, i32* %B, i32 %N) {
|
|||
; CHECK: vector.scevcheck:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i2
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i2 [[TMP1]], 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i2 0, [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = sub i2 0, [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i2 [[TMP3]], 0
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i2 [[TMP2]], 0
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
|||
;
|
||||
; NO-IC: vector.body:
|
||||
; NO-IC: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
|
||||
; NO-IC: %offset.idx = add i64 %index, 1
|
||||
; NO-IC: %offset.idx = add i64 1, %index
|
||||
; NO-IC: %[[T2:.+]] = add i64 %offset.idx, 0
|
||||
; NO-IC: %[[T3:.+]] = add i64 %offset.idx, 4
|
||||
; NO-IC: %[[T4:.+]] = add nuw nsw i64 %[[T2]], %tmp0
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ define void @f1(i16* noalias %a,
|
|||
; LV-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
|
||||
; LV-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
|
||||
; LV-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
|
||||
; LV-NEXT: [[TMP2:%.*]] = add i32 [[MUL_RESULT]], 0
|
||||
; LV-NEXT: [[TMP2:%.*]] = add i32 0, [[MUL_RESULT]]
|
||||
; LV-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]
|
||||
; LV-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 0
|
||||
; LV-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP2]], 0
|
||||
|
|
@ -271,7 +271,7 @@ define void @f3(i16* noalias %a,
|
|||
; LV-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
|
||||
; LV-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
|
||||
; LV-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
|
||||
; LV-NEXT: [[TMP2:%.*]] = add i32 [[MUL_RESULT]], 0
|
||||
; LV-NEXT: [[TMP2:%.*]] = add i32 0, [[MUL_RESULT]]
|
||||
; LV-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]
|
||||
; LV-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP3]], 0
|
||||
; LV-NEXT: [[TMP5:%.*]] = icmp slt i32 [[TMP2]], 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue