forked from OSchip/llvm-project
Add overall description, file comments, some structure
llvm-svn: 204479
This commit is contained in:
Renato Golin
parent
3a12fc6a07
commit
1014ec3bcb
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@ -32,86 +32,201 @@ LLVM BackEnds
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of its purpose with a list of users, output generated from generic input, and
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finally why it needed a new backend (in case there's something similar).
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Emitter
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-------
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Overall, each backend will take the same TableGen file type and transform into
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similar output for different targets/uses. There is an implicit contract between
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the TableGen files, the back-ends and their users.
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Generate machine code emitter.
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For instance, a global contract is that each back-end produces macro-guarded
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sections. Based on whether the file is included by a header or a source file,
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or even in which context of each file the include is being used, you have
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todefine a macro just before including it, to get the right output:
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.. code-block:: c++
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#define GET_REGINFO_TARGET_DESC
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#include "ARMGenRegisterInfo.inc"
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And just part of the generated file would be included. This is useful if
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you need the same information in multiple formats (instantiation, initialization,
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getter/setter functions, etc) from the same source TableGen file without having
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to re-compile the TableGen file multiple times.
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Sometimes, multiple macros might be defined before the same include file to
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output multiple blocks:
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.. code-block:: c++
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#define GET_REGISTER_MATCHER
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#define GET_SUBTARGET_FEATURE_NAME
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#define GET_MATCHER_IMPLEMENTATION
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#include "ARMGenAsmMatcher.inc"
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The macros will be undef'd automatically as they're used, in the include file.
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On all LLVM back-ends, the ``llvm-tblgen`` binary will be executed on the root
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TableGen file ``<Target>.td``, which should include all others. This guarantees
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that all information needed is accessible, and that no duplication is needed
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in the TbleGen files.
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CodeEmitter
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-----------
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**Purpose**: CodeEmitterGen uses the descriptions of instructions and their fields to
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construct an automated code emitter: a function that, given a MachineInstr,
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returns the (currently, 32-bit unsigned) value of the instruction.
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**Output**: C++ code, implementing the target's CodeEmitter
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class by overriding the virtual functions as ``<Target>CodeEmitter::function()``.
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**Usage**: Used to include directly at the end of ``<Target>CodeEmitter.cpp``, and
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with option `-mc-emitter` to be included in ``<Target>MCCodeEmitter.cpp``.
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RegisterInfo
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------------
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Generate registers and register classes info.
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**Purpose**: This tablegen backend is responsible for emitting a description of a target
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register file for a code generator. It uses instances of the Register,
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RegisterAliases, and RegisterClass classes to gather this information.
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**Output**: C++ code with enums and structures representing the register mappings,
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properties, masks, etc.
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**Usage**: Both on ``<Target>BaseRegisterInfo`` and ``<Target>MCTargetDesc`` (headers
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and source files) with macros defining in which they are for declaration vs.
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initialization issues.
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InstrInfo
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---------
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Generate instruction descriptions.
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**Purpose**: This tablegen backend is responsible for emitting a description of the target
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instruction set for the code generator. (what are the differences from CodeEmitter?)
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**Output**: C++ code with enums and structures representing the register mappings,
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properties, masks, etc.
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**Usage**: Both on ``<Target>BaseInstrInfo`` and ``<Target>MCTargetDesc`` (headers
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and source files) with macros defining in which they are for declaration vs.
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AsmWriter
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---------
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Generate calling convention descriptions.
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**Purpose**: Emits an assembly printer for the current target.
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**Output**: Implementation of ``<Target>InstPrinter::printInstruction()``, among
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other things.
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**Usage**: Included directly into ``InstPrinter/<Target>InstPrinter.cpp``.
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AsmMatcher
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----------
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Generate assembly writer.
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**Purpose**: Emits a target specifier matcher for
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converting parsed assembly operands in the MCInst structures. It also
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emits a matcher for custom operand parsing. Extensive documentation is
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written on the ``AsmMatcherEmitter.cpp`` file.
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**Output**: Assembler parsers' matcher functions, declarations, etc.
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**Usage**: Used in back-ends' ``AsmParser/<Target>AsmParser.cpp`` for
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building the AsmParser class.
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Disassembler
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------------
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Generate disassembler.
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**Purpose**: Contains disassembler table emitters for various
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architectures. Extensive documentation is written on the
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``DisassemblerEmitter.cpp`` file.
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**Output**: Decoding tables, static decoding functions, etc.
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**Usage**: Directly included in ``Disassembler/<Target>Disassembler.cpp``
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to cater for all default decodings, after all hand-made ones.
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PseudoLowering
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--------------
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Generate pseudo instruction lowering.
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**Purpose**: Generate pseudo instruction lowering.
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**Output**: Implements ``ARMAsmPrinter::emitPseudoExpansionLowering()``.
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**Usage**: Included directly into ``<Target>AsmPrinter.cpp``.
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CallingConv
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-----------
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Generate assembly instruction matcher.
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**Purpose**: Responsible for emitting descriptions of the calling
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conventions supported by this target.
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**Output**: Implement static functions to deal with calling conventions
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chained by matching styles, returning false on no match.
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**Usage**: Used in ISelLowering and FastIsel as function pointers to
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implementation returned by a CC sellection function.
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DAGISel
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-------
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Generate a DAG instruction selector.
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**Purpose**: Generate a DAG instruction selector.
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**Output**: Creates huge functions for automating DAG selection.
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**Usage**: Included in ``<Target>ISelDAGToDAG.cpp`` inside the target's
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implementation of ``SelectionDAGISel``.
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DFAPacketizer
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-------------
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Generate DFA Packetizer for VLIW targets.
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**Purpose**: This class parses the Schedule.td file and produces an API that
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can be used to reason about whether an instruction can be added to a packet
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on a VLIW architecture. The class internally generates a deterministic finite
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automaton (DFA) that models all possible mappings of machine instructions
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to functional units as instructions are added to a packet.
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**Output**: Scheduling tables for GPU back-ends (Hexagon, AMD).
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**Usage**: Included directly on ``<Target>InstrInfo.cpp``.
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FastISel
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--------
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Generate a "fast" instruction selector.
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**Purpose**: This tablegen backend emits code for use by the "fast"
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instruction selection algorithm. See the comments at the top of
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lib/CodeGen/SelectionDAG/FastISel.cpp for background. This file
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scans through the target's tablegen instruction-info files
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and extracts instructions with obvious-looking patterns, and it emits
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code to look up these instructions by type and operator.
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**Output**: Generates ``Predicate`` and ``FastEmit`` methods.
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**Usage**: Implements private methods of the targets' implementation
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of ``FastISel`` class.
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Subtarget
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---------
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Generate subtarget enumerations.
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**Purpose**: Generate subtarget enumerations.
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**Output**: Enums, globals, local tables for sub-target information.
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**Usage**: Populates ``<Target>Subtarget`` and
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``MCTargetDesc/<Target>MCTargetDesc`` files (both headers and source).
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Intrinsic
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---------
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Generate intrinsic information.
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TgtIntrinsic
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------------
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Generate target intrinsic information.
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**Purpose**: Generate (target) intrinsic information.
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OptParserDefs
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-------------
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Print enum values for a class.
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**Purpose**: Print enum values for a class.
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CTags
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-----
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Generate ctags-compatible index.
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**Purpose**: This tablegen backend emits an index of definitions in ctags(1)
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format. A helper script, utils/TableGen/tdtags, provides an easier-to-use
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interface; run 'tdtags -H' for documentation.
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Clang BackEnds
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==============
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