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these cases are autogenerated 

llvm-svn: 25238
This commit is contained in:
Chris Lattner 2006-01-12 02:01:45 +00:00
parent 44416f92f1
commit 1014b38404
1 changed files with 0 additions and 28 deletions
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28
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -973,34 +973,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
// Other cases are autogenerated.
break;
}
case ISD::FNEG: {
SDOperand Val = Select(N->getOperand(0));
MVT::ValueType Ty = N->getValueType(0);
if (N->getOperand(0).Val->hasOneUse()) {
unsigned Opc;
switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
default: Opc = 0; break;
case PPC::FABSS: Opc = PPC::FNABSS; break;
case PPC::FABSD: Opc = PPC::FNABSD; break;
case PPC::FMADD: Opc = PPC::FNMADD; break;
case PPC::FMADDS: Opc = PPC::FNMADDS; break;
case PPC::FMSUB: Opc = PPC::FNMSUB; break;
case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
}
// If we inverted the opcode, then emit the new instruction with the
// inverted opcode and the original instruction's operands. Otherwise,
// fall through and generate a fneg instruction.
if (Opc) {
if (Opc == PPC::FNABSS || Opc == PPC::FNABSD)
return CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
else
return CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
Val.getOperand(1), Val.getOperand(2));
}
}
// Other cases are autogenerated.
break;
}
case ISD::SELECT_CC: {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();