[NFC][AMDGPU] Remove some generic pointers in memory-legalizer tests

These tests implicitly depend on the target supporting generic pointers,
so to prepare for testing them on GFX6 (which lacks FLAT) remove the
dependency where possible.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D91666
This commit is contained in:
Scott Linder 2020-11-18 20:52:17 +00:00
parent cd3c22c47e
commit 0fe4b8e4b5
2 changed files with 24 additions and 24 deletions

View File

@ -454,10 +454,10 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_private_0(
i32 addrspace(5)* %in, i32* %out) {
i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
entry:
%val = load i32, i32 addrspace(5)* %in, align 4, !nontemporal !0
store i32 %val, i32* %out
store i32 %val, i32 addrspace(1)* %out
ret void
}
@ -469,12 +469,12 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_private_1(
i32 addrspace(5)* %in, i32* %out) {
i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid
%val = load i32, i32 addrspace(5)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32* %out
store i32 %val, i32 addrspace(1)* %out
ret void
}
@ -485,10 +485,10 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_global_0(
i32 addrspace(1)* %in, i32* %out) {
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%val = load i32, i32 addrspace(1)* %in, align 4, !nontemporal !0
store i32 %val, i32* %out
store i32 %val, i32 addrspace(1)* %out
ret void
}
@ -501,12 +501,12 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_global_1(
i32 addrspace(1)* %in, i32* %out) {
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
%val = load i32, i32 addrspace(1)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32* %out
store i32 %val, i32 addrspace(1)* %out
ret void
}
@ -517,10 +517,10 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_local_0(
i32 addrspace(3)* %in, i32* %out) {
i32 addrspace(3)* %in, i32 addrspace(1)* %out) {
entry:
%val = load i32, i32 addrspace(3)* %in, align 4, !nontemporal !0
store i32 %val, i32* %out
store i32 %val, i32 addrspace(1)* %out
ret void
}
@ -531,12 +531,12 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_local_1(
i32 addrspace(3)* %in, i32* %out) {
i32 addrspace(3)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid
%val = load i32, i32 addrspace(3)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32* %out
store i32 %val, i32 addrspace(1)* %out
ret void
}

View File

@ -321,9 +321,9 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_private_0(
i32* %in, i32 addrspace(5)* %out) {
i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
entry:
%val = load i32, i32* %in, align 4
%val = load i32, i32 addrspace(1)* %in, align 4
store i32 %val, i32 addrspace(5)* %out, !nontemporal !0
ret void
}
@ -336,10 +336,10 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_private_1(
i32* %in, i32 addrspace(5)* %out) {
i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32* %in, align 4
%val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid
store i32 %val, i32 addrspace(5)* %out.gep, !nontemporal !0
ret void
@ -354,9 +354,9 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_global_0(
i32* %in, i32 addrspace(1)* %out) {
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%val = load i32, i32* %in, align 4
%val = load i32, i32 addrspace(1)* %in, align 4
store i32 %val, i32 addrspace(1)* %out, !nontemporal !0
ret void
}
@ -370,10 +370,10 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_global_1(
i32* %in, i32 addrspace(1)* %out) {
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32* %in, align 4
%val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0
ret void
@ -386,9 +386,9 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_local_0(
i32* %in, i32 addrspace(3)* %out) {
i32 addrspace(1)* %in, i32 addrspace(3)* %out) {
entry:
%val = load i32, i32* %in, align 4
%val = load i32, i32 addrspace(1)* %in, align 4
store i32 %val, i32 addrspace(3)* %out, !nontemporal !0
ret void
}
@ -400,10 +400,10 @@ entry:
; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_local_1(
i32* %in, i32 addrspace(3)* %out) {
i32 addrspace(1)* %in, i32 addrspace(3)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32* %in, align 4
%val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid
store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0
ret void