forked from OSchip/llvm-project
parent
4cf8fe31bb
commit
0fb303d3c0
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@ -921,8 +921,37 @@ void MachineVerifier::verifyLiveIntervals() {
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report("Live range at def has different valno", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " where valno #" << DefVNI->id << " is live.\n";
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continue;
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}
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
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if (!MBB) {
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report("Invalid definition index", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
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continue;
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}
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if (VNI->isPHIDef()) {
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if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
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report("PHIDef value is not defined at MBB start", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< ", not at the beginning of BB#" << MBB->getNumber() << '\n';
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}
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} else {
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// Non-PHI def.
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if (!VNI->def.isDef()) {
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report("Non-PHI def must be at a DEF slot", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
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}
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const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
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if (!MI) {
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report("No instruction at def index", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
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} else if (!MI->modifiesRegister(LI.reg, TRI)) {
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report("Defining instruction does not modify register", MI);
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*OS << "Valno #" << VNI->id << " in " << LI << '\n';
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}
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}
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}
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for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
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