maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[RISCV] Add nounwind to remove some cfi directives from test CHECKs. NFC

This commit is contained in:
Craig Topper 2022-01-08 12:27:46 -08:00
parent db4cb4668b
commit 0f9f17869f
3 changed files with 9 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
llvm/test/CodeGen/RISCV/double-convert.ll
View File

@ -310,11 +310,10 @@ define i32 @fcvt_wu_d(double %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) {
define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
@ -341,9 +340,7 @@ define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) {
; RV32I-LABEL: fcvt_wu_d_multiple_use:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: li a0, 1
@ -358,9 +355,7 @@ define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) {
; RV64I-LABEL: fcvt_wu_d_multiple_use:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call __fixunsdfsi@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: li a0, 1
@ -1443,7 +1438,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
}
; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) nounwind {
; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1
@ -1461,13 +1456,9 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
; RV32I-LABEL: fcvt_d_w_demanded_bits:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: addi s1, a0, 1
; RV32I-NEXT: mv a0, s1
@ -1484,13 +1475,9 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
; RV64I-LABEL: fcvt_d_w_demanded_bits:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: addiw s1, a0, 1
; RV64I-NEXT: mv a0, s1
@ -1509,7 +1496,7 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
}
; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) {
define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) nounwind {
; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi a0, a0, 1
@ -1527,13 +1514,9 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) {
; RV32I-LABEL: fcvt_d_wu_demanded_bits:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: addi s1, a0, 1
; RV32I-NEXT: mv a0, s1
@ -1550,13 +1533,9 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) {
; RV64I-LABEL: fcvt_d_wu_demanded_bits:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: addiw s1, a0, 1
; RV64I-NEXT: mv a0, s1

26
llvm/test/CodeGen/RISCV/float-convert.ll
View File

@ -202,7 +202,7 @@ define i32 @fcvt_wu_s(float %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
; RV32IF-LABEL: fcvt_wu_s_multiple_use:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
@ -228,9 +228,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
; RV32I-LABEL: fcvt_wu_s_multiple_use:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call __fixunssfsi@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: li a0, 1
@ -245,9 +243,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
; RV64I-LABEL: fcvt_wu_s_multiple_use:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call __fixunssfsi@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: li a0, 1
@ -1234,7 +1230,7 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
}
; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) nounwind {
; RV32IF-LABEL: fcvt_s_w_demanded_bits:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1
@ -1252,13 +1248,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
; RV32I-LABEL: fcvt_s_w_demanded_bits:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: addi s1, a0, 1
; RV32I-NEXT: mv a0, s1
@ -1274,13 +1266,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
; RV64I-LABEL: fcvt_s_w_demanded_bits:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: addiw s1, a0, 1
; RV64I-NEXT: mv a0, s1
@ -1299,7 +1287,7 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
}
; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) nounwind {
; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, a0, 1
@ -1317,13 +1305,9 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
; RV32I-LABEL: fcvt_s_wu_demanded_bits:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: addi s1, a0, 1
; RV32I-NEXT: mv a0, s1
@ -1339,13 +1323,9 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
; RV64I-LABEL: fcvt_s_wu_demanded_bits:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: addiw s1, a0, 1
; RV64I-NEXT: mv a0, s1

26
llvm/test/CodeGen/RISCV/half-convert.ll
View File

@ -672,7 +672,7 @@ define i32 @fcvt_wu_h(half %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) {
define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) nounwind {
; RV32IZFH-LABEL: fcvt_wu_h_multiple_use:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
@ -716,9 +716,7 @@ define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) {
; RV32I-LABEL: fcvt_wu_h_multiple_use:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
@ -737,9 +735,7 @@ define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) {
; RV64I-LABEL: fcvt_wu_h_multiple_use:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
@ -2265,7 +2261,7 @@ define i16 @bitcast_i16_h(half %a) nounwind {
}
; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) nounwind {
; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1
@ -2297,13 +2293,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
; RV32I-LABEL: fcvt_h_w_demanded_bits:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: addi s1, a0, 1
; RV32I-NEXT: mv a0, s1
@ -2320,13 +2312,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
; RV64I-LABEL: fcvt_h_w_demanded_bits:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: addiw s1, a0, 1
; RV64I-NEXT: mv a0, s1
@ -2346,7 +2334,7 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
}
; Make sure we select W version of addi on RV64.
define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) nounwind {
; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, a0, 1
@ -2378,13 +2366,9 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
; RV32I-LABEL: fcvt_h_wu_demanded_bits:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: addi s1, a0, 1
; RV32I-NEXT: mv a0, s1
@ -2401,13 +2385,9 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
; RV64I-LABEL: fcvt_h_wu_demanded_bits:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: addiw s1, a0, 1
; RV64I-NEXT: mv a0, s1