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AMDGPU: Fix using 2 different enums for same operand flags 

These enums are really for the same namespace of flags set on
arbitrary MachineOperands, so merge them to avoid value collisions.

llvm-svn: 362640
This commit is contained in:
Matt Arsenault 2019-06-05 20:32:25 +00:00
parent ecf3ae4a70
commit 0f8a764e8f
3 changed files with 8 additions and 11 deletions
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4
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
View File

@ -112,10 +112,10 @@ const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD)
if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD)
return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD);
assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD);
return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
}

4
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -1532,7 +1532,7 @@ unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub0)
.addReg(PCReg, 0, AMDGPU::sub0)
.addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_FORWARD);
.addMBB(&DestBB, MO_LONG_BRANCH_FORWARD);
BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub1)
.addReg(PCReg, 0, AMDGPU::sub1)
@ -1542,7 +1542,7 @@ unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub0)
.addReg(PCReg, 0, AMDGPU::sub0)
.addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_BACKWARD);
.addMBB(&DestBB, MO_LONG_BRANCH_BACKWARD);
BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub1)
.addReg(PCReg, 0, AMDGPU::sub1)

11
llvm/lib/Target/AMDGPU/SIInstrInfo.h
View File

@ -157,7 +157,10 @@ public:
MO_REL32 = 4,
MO_REL32_LO = 4,
// MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
MO_REL32_HI = 5
MO_REL32_HI = 5,
MO_LONG_BRANCH_FORWARD = 6,
MO_LONG_BRANCH_BACKWARD = 7
};
explicit SIInstrInfo(const GCNSubtarget &ST);
@ -1030,12 +1033,6 @@ namespace AMDGPU {
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
// For MachineOperands.
enum TargetFlags {
TF_LONG_BRANCH_FORWARD = 1 << 0,
TF_LONG_BRANCH_BACKWARD = 1 << 1
};
} // end namespace AMDGPU
namespace SI {