forked from OSchip/llvm-project
[AArch64] Add extra codegen tests. NFC
This adds some extra codegen tests for abs and hadd, regenerating some of the existing tests with updated check lines.
This commit is contained in:
David Green
parent
2d8cb8205a
commit
0f88328867
File diff suppressed because it is too large
Load Diff
|
|
@ -701,6 +701,122 @@ define void @testLowerToUHADD4s(<4 x i32> %src1, <4 x i32> %src2, <4 x i32>* %de
|
|||
ret void
|
||||
}
|
||||
|
||||
|
||||
define <4 x i32> @hadd16_sext_asr(<4 x i16> %src1, <4 x i16> %src2) nounwind {
|
||||
; CHECK-LABEL: hadd16_sext_asr:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: saddl.4s v0, v0, v1
|
||||
; CHECK-NEXT: sshr.4s v0, v0, #1
|
||||
; CHECK-NEXT: ret
|
||||
%zextsrc1 = sext <4 x i16> %src1 to <4 x i32>
|
||||
%zextsrc2 = sext <4 x i16> %src2 to <4 x i32>
|
||||
%add = add <4 x i32> %zextsrc1, %zextsrc2
|
||||
%resulti16 = ashr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
|
||||
ret <4 x i32> %resulti16
|
||||
}
|
||||
|
||||
define <4 x i32> @hadd16_zext_asr(<4 x i16> %src1, <4 x i16> %src2) nounwind {
|
||||
; CHECK-LABEL: hadd16_zext_asr:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddl.4s v0, v0, v1
|
||||
; CHECK-NEXT: ushr.4s v0, v0, #1
|
||||
; CHECK-NEXT: ret
|
||||
%zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
|
||||
%zextsrc2 = zext <4 x i16> %src2 to <4 x i32>
|
||||
%add = add <4 x i32> %zextsrc1, %zextsrc2
|
||||
%resulti16 = ashr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
|
||||
ret <4 x i32> %resulti16
|
||||
}
|
||||
|
||||
define <4 x i32> @hadd16_sext_lsr(<4 x i16> %src1, <4 x i16> %src2) nounwind {
|
||||
; CHECK-LABEL: hadd16_sext_lsr:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: saddl.4s v0, v0, v1
|
||||
; CHECK-NEXT: ushr.4s v0, v0, #1
|
||||
; CHECK-NEXT: ret
|
||||
%zextsrc1 = sext <4 x i16> %src1 to <4 x i32>
|
||||
%zextsrc2 = sext <4 x i16> %src2 to <4 x i32>
|
||||
%add = add <4 x i32> %zextsrc1, %zextsrc2
|
||||
%resulti16 = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
|
||||
ret <4 x i32> %resulti16
|
||||
}
|
||||
|
||||
define <4 x i32> @hadd16_zext_lsr(<4 x i16> %src1, <4 x i16> %src2) nounwind {
|
||||
; CHECK-LABEL: hadd16_zext_lsr:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddl.4s v0, v0, v1
|
||||
; CHECK-NEXT: ushr.4s v0, v0, #1
|
||||
; CHECK-NEXT: ret
|
||||
%zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
|
||||
%zextsrc2 = zext <4 x i16> %src2 to <4 x i32>
|
||||
%add = add <4 x i32> %zextsrc1, %zextsrc2
|
||||
%resulti16 = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
|
||||
ret <4 x i32> %resulti16
|
||||
}
|
||||
|
||||
|
||||
|
||||
define <4 x i64> @hadd32_sext_asr(<4 x i32> %src1, <4 x i32> %src2) nounwind {
|
||||
; CHECK-LABEL: hadd32_sext_asr:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: saddl.2d v2, v0, v1
|
||||
; CHECK-NEXT: saddl2.2d v0, v0, v1
|
||||
; CHECK-NEXT: sshr.2d v1, v0, #1
|
||||
; CHECK-NEXT: sshr.2d v0, v2, #1
|
||||
; CHECK-NEXT: ret
|
||||
%zextsrc1 = sext <4 x i32> %src1 to <4 x i64>
|
||||
%zextsrc2 = sext <4 x i32> %src2 to <4 x i64>
|
||||
%add = add <4 x i64> %zextsrc1, %zextsrc2
|
||||
%resulti32 = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
|
||||
ret <4 x i64> %resulti32
|
||||
}
|
||||
|
||||
define <4 x i64> @hadd32_zext_asr(<4 x i32> %src1, <4 x i32> %src2) nounwind {
|
||||
; CHECK-LABEL: hadd32_zext_asr:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddl.2d v2, v0, v1
|
||||
; CHECK-NEXT: uaddl2.2d v0, v0, v1
|
||||
; CHECK-NEXT: ushr.2d v1, v0, #1
|
||||
; CHECK-NEXT: ushr.2d v0, v2, #1
|
||||
; CHECK-NEXT: ret
|
||||
%zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
|
||||
%zextsrc2 = zext <4 x i32> %src2 to <4 x i64>
|
||||
%add = add <4 x i64> %zextsrc1, %zextsrc2
|
||||
%resulti32 = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
|
||||
ret <4 x i64> %resulti32
|
||||
}
|
||||
|
||||
define <4 x i64> @hadd32_sext_lsr(<4 x i32> %src1, <4 x i32> %src2) nounwind {
|
||||
; CHECK-LABEL: hadd32_sext_lsr:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: saddl.2d v2, v0, v1
|
||||
; CHECK-NEXT: saddl2.2d v0, v0, v1
|
||||
; CHECK-NEXT: ushr.2d v1, v0, #1
|
||||
; CHECK-NEXT: ushr.2d v0, v2, #1
|
||||
; CHECK-NEXT: ret
|
||||
%zextsrc1 = sext <4 x i32> %src1 to <4 x i64>
|
||||
%zextsrc2 = sext <4 x i32> %src2 to <4 x i64>
|
||||
%add = add <4 x i64> %zextsrc1, %zextsrc2
|
||||
%resulti32 = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
|
||||
ret <4 x i64> %resulti32
|
||||
}
|
||||
|
||||
define <4 x i64> @hadd32_zext_lsr(<4 x i32> %src1, <4 x i32> %src2) nounwind {
|
||||
; CHECK-LABEL: hadd32_zext_lsr:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddl.2d v2, v0, v1
|
||||
; CHECK-NEXT: uaddl2.2d v0, v0, v1
|
||||
; CHECK-NEXT: ushr.2d v1, v0, #1
|
||||
; CHECK-NEXT: ushr.2d v0, v2, #1
|
||||
; CHECK-NEXT: ret
|
||||
%zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
|
||||
%zextsrc2 = zext <4 x i32> %src2 to <4 x i64>
|
||||
%add = add <4 x i64> %zextsrc1, %zextsrc2
|
||||
%resulti32 = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
|
||||
ret <4 x i64> %resulti32
|
||||
}
|
||||
|
||||
|
||||
declare <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
|
||||
declare i64 @llvm.abs.i64(i64, i1 immarg)
|
||||
|
||||
define i64@neg_abs(i64 %x) {
|
||||
; CHECK-LABEL: neg_abs:
|
||||
define i64 @neg_abs64(i64 %x) {
|
||||
; CHECK-LABEL: neg_abs64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: cmp x0, #0 // =0
|
||||
; CHECK-NEXT: cneg x8, x0, mi
|
||||
|
|
@ -15,3 +15,95 @@ define i64@neg_abs(i64 %x) {
|
|||
%neg = sub nsw i64 0, %abs
|
||||
ret i64 %neg
|
||||
}
|
||||
|
||||
declare i32 @llvm.abs.i32(i32, i1 immarg)
|
||||
|
||||
define i32 @neg_abs32(i32 %x) {
|
||||
; CHECK-LABEL: neg_abs32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: cmp w0, #0 // =0
|
||||
; CHECK-NEXT: cneg w8, w0, mi
|
||||
; CHECK-NEXT: neg w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
|
||||
%neg = sub nsw i32 0, %abs
|
||||
ret i32 %neg
|
||||
}
|
||||
|
||||
declare i16 @llvm.abs.i16(i16, i1 immarg)
|
||||
|
||||
define i16 @neg_abs16(i16 %x) {
|
||||
; CHECK-LABEL: neg_abs16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sbfx w8, w0, #15, #1
|
||||
; CHECK-NEXT: eor w9, w0, w8
|
||||
; CHECK-NEXT: sub w0, w8, w9
|
||||
; CHECK-NEXT: ret
|
||||
%abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
|
||||
%neg = sub nsw i16 0, %abs
|
||||
ret i16 %neg
|
||||
}
|
||||
|
||||
|
||||
declare i128 @llvm.abs.i128(i128, i1 immarg)
|
||||
|
||||
define i128 @neg_abs128(i128 %x) {
|
||||
; CHECK-LABEL: neg_abs128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: asr x8, x1, #63
|
||||
; CHECK-NEXT: eor x10, x0, x8
|
||||
; CHECK-NEXT: eor x9, x1, x8
|
||||
; CHECK-NEXT: subs x0, x8, x10
|
||||
; CHECK-NEXT: sbcs x1, x8, x9
|
||||
; CHECK-NEXT: ret
|
||||
%abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
|
||||
%neg = sub nsw i128 0, %abs
|
||||
ret i128 %neg
|
||||
}
|
||||
|
||||
|
||||
|
||||
define i64 @abs64(i64 %x) {
|
||||
; CHECK-LABEL: abs64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: cmp x0, #0 // =0
|
||||
; CHECK-NEXT: cneg x0, x0, mi
|
||||
; CHECK-NEXT: ret
|
||||
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
|
||||
ret i64 %abs
|
||||
}
|
||||
|
||||
define i32 @abs32(i32 %x) {
|
||||
; CHECK-LABEL: abs32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: cmp w0, #0 // =0
|
||||
; CHECK-NEXT: cneg w0, w0, mi
|
||||
; CHECK-NEXT: ret
|
||||
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
|
||||
ret i32 %abs
|
||||
}
|
||||
|
||||
define i16 @abs16(i16 %x) {
|
||||
; CHECK-LABEL: abs16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sxth w8, w0
|
||||
; CHECK-NEXT: cmp w8, #0 // =0
|
||||
; CHECK-NEXT: cneg w0, w8, mi
|
||||
; CHECK-NEXT: ret
|
||||
%abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
|
||||
ret i16 %abs
|
||||
}
|
||||
|
||||
define i128 @abs128(i128 %x) {
|
||||
; CHECK-LABEL: abs128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: negs x8, x0
|
||||
; CHECK-NEXT: ngcs x9, x1
|
||||
; CHECK-NEXT: cmp x1, #0 // =0
|
||||
; CHECK-NEXT: csel x0, x8, x0, lt
|
||||
; CHECK-NEXT: csel x1, x9, x1, lt
|
||||
; CHECK-NEXT: ret
|
||||
%abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
|
||||
ret i128 %abs
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue