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[Hexagon] Removing old variants of instructions and updating references. 

llvm-svn: 224612
This commit is contained in:
Colin LeMahieu 2014-12-19 20:29:29 +00:00
parent 0428a5786e
commit 0f850bde0e
7 changed files with 15 additions and 161 deletions
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6
llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
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@ -168,18 +168,18 @@ void HexagonFixupHwLoops::convertLoopInstr(MachineFunction &MF,
// First, set the LC0 with the trip count.
if (MII->getOperand(1).isReg()) {
// Trip count is a register
BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
BuildMI(*MBB, MII, DL, TII->get(Hexagon::A2_tfrrcr), Hexagon::LC0)
.addReg(MII->getOperand(1).getReg());
} else {
// Trip count is an immediate.
BuildMI(*MBB, MII, DL, TII->get(Hexagon::A2_tfrsi), Scratch)
.addImm(MII->getOperand(1).getImm());
BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
BuildMI(*MBB, MII, DL, TII->get(Hexagon::A2_tfrrcr), Hexagon::LC0)
.addReg(Scratch);
}
// Then, set the SA0 with the loop start address.
BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
.addMBB(MII->getOperand(0).getMBB());
BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0)
BuildMI(*MBB, MII, DL, TII->get(Hexagon::A2_tfrrcr), Hexagon::SA0)
.addReg(Scratch);
}

2
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
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@ -1195,7 +1195,7 @@ MachineInstr *HexagonHardwareLoops::defWithImmediate(unsigned R) {
unsigned DOpc = DI->getOpcode();
switch (DOpc) {
case Hexagon::A2_tfrsi:
case Hexagon::TFRI64:
case Hexagon::A2_tfrpi:
case Hexagon::CONST32_Int_Real:
case Hexagon::CONST64_Int_Real:
return DI;

2
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -1334,7 +1334,7 @@ SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
// Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
// Rd and Rd' are assigned to the same register
SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_ADD_rr, dl, MVT::i32,
SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
N->getOperand(1),
Src1->getOperand(0),
Src1->getOperand(1));

2
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -449,7 +449,7 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
Hexagon::IntRegsRegClass.contains(SrcReg)) {
BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
return;
}
if (Hexagon::PredRegsRegClass.contains(SrcReg) &&

160
llvm/lib/Target/Hexagon/HexagonInstrInfo.td
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@ -614,11 +614,6 @@ let isExtendable = 1, opExtendable = 1, opExtentBits = 6 in
def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
"$dst = #$src1">;
// Transfer control register.
let hasSideEffects = 0 in
def TFCR : CRInst<(outs CtrRegs:$dst), (ins IntRegs:$src1),
"$dst = $src1",
[]>;
//===----------------------------------------------------------------------===//
// ALU32/ALU -
//===----------------------------------------------------------------------===//
@ -835,14 +830,6 @@ def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
return XformUToUM1Imm(imm);
}]>;
def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
"$dst = cl0($src1)",
[(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
"$dst = ct0($src1)",
[(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
"$dst = cl0($src1)",
[(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
@ -851,11 +838,6 @@ def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
"$dst = ct0($src1)",
[(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
"$dst = tstbit($src1, $src2)",
[(set (i1 PredRegs:$dst),
(setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
//===----------------------------------------------------------------------===//
// ALU32/PRED -
//===----------------------------------------------------------------------===//
@ -3160,58 +3142,6 @@ def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
let Inst{4-0} = Rd;
}
// Shift by immediate and add.
let AddedComplexity = 100 in
def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
u3Imm:$src3),
"$dst = addasl($src1, $src2, #$src3)",
[(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
(shl (i32 IntRegs:$src2),
u3ImmPred:$src3)))]>;
// Shift by register.
def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
"$dst = asl($src1, $src2)",
[(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
"$dst = asr($src1, $src2)",
[(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
"$dst = lsl($src1, $src2)",
[(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
"$dst = lsr($src1, $src2)",
[(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
(i32 IntRegs:$src2)))]>;
def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
"$dst = asl($src1, $src2)",
[(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
(i32 IntRegs:$src2)))]>;
def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
"$dst = lsl($src1, $src2)",
[(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
(i32 IntRegs:$src2)))]>;
def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
IntRegs:$src2),
"$dst = asr($src1, $src2)",
[(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
(i32 IntRegs:$src2)))]>;
def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
IntRegs:$src2),
"$dst = lsr($src1, $src2)",
[(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
(i32 IntRegs:$src2)))]>;
//===----------------------------------------------------------------------===//
// STYPE/SHIFT -
//===----------------------------------------------------------------------===//
@ -3237,14 +3167,15 @@ def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
//===----------------------------------------------------------------------===//
// SYSTEM/USER +
//===----------------------------------------------------------------------===//
def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
[SDNPHasChain]>;
def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
let hasSideEffects = 1, isSolo = 1 in
let hasSideEffects = 1, isSoloAX = 1, isCodeGenOnly = 0 in
def BARRIER : SYSInst<(outs), (ins),
"barrier",
[(HexagonBARRIER)]>;
[(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
let Inst{31-28} = 0b1010;
let Inst{27-21} = 0b1000000;
}
//===----------------------------------------------------------------------===//
// SYSTEM/SUPER -
@ -3421,12 +3352,6 @@ def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
let Inst{20-16} = Rs;
}
// TFRI64 - assembly mapped.
let isReMaterializable = 1 in
def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
"$dst = #$src1",
[(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
let AddedComplexity = 100, isPredicated = 1 in
def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
@ -4751,79 +4676,6 @@ def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
}
// Multi-class for logical operators :
// Shift by immediate/register and accumulate/logical
multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
def _ri : SInst_acc<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
!strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
[(set (i32 IntRegs:$dst),
(OpNode2 (i32 IntRegs:$src1),
(OpNode1 (i32 IntRegs:$src2),
u5ImmPred:$src3)))],
"$src1 = $dst">;
def d_ri : SInst_acc<(outs DoubleRegs:$dst),
(ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
!strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
[(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
(OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
"$src1 = $dst">;
}
// Multi-class for logical operators :
// Shift by register and accumulate/logical (32/64 bits)
multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
def _rr : SInst_acc<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
!strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
[(set (i32 IntRegs:$dst),
(OpNode2 (i32 IntRegs:$src1),
(OpNode1 (i32 IntRegs:$src2),
(i32 IntRegs:$src3))))],
"$src1 = $dst">;
def d_rr : SInst_acc<(outs DoubleRegs:$dst),
(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
!strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
[(set (i64 DoubleRegs:$dst),
(OpNode2 (i64 DoubleRegs:$src1),
(OpNode1 (i64 DoubleRegs:$src2),
(i32 IntRegs:$src3))))],
"$src1 = $dst">;
}
multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
let AddedComplexity = 100 in
defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
}
multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
let AddedComplexity = 100 in
defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
}
multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
let AddedComplexity = 100 in
defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
}
defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
xtype_xor_imm<"asl", shl>;
defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
xtype_xor_imm<"lsr", srl>;
defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
defm LSL : basic_xtype_reg<"lsl", shl>;
// Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
(i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;

2
llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -118,7 +118,7 @@ def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd),
// Preserve the TSTBIT generation
def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
(i32 IntRegs:$src1))), 0)))),
(i32 (C2_muxii (i1 (TSTBIT_rr (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
(i32 (C2_muxii (i1 (S2_tstbit_r (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
1, 0))>;
// Interfered with tstbit generation, above pattern preserves, see : tstbit.ll

2
llvm/test/MC/Disassembler/Hexagon/system_user.txt
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@ -1,4 +1,6 @@
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
0x00 0xc0 0x00 0xa8
# CHECK: barrier
0x00 0xc0 0x51 0x62
# CHECK: trace(r17)