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VLDR fixups need special handling under Thumb. While the encoding is the same, 

the order of the bytes in the data stream is flipped around.

llvm-svn: 121215
This commit is contained in:
Owen Anderson 2010-12-08 00:18:36 +00:00
parent 8811c3a72e
commit 0f7142d808
3 changed files with 23 additions and 2 deletions
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12
llvm/lib/Target/ARM/ARMAsmBackend.cpp
View File

@ -115,6 +115,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
Binary = ((Binary & 0x7ff) << 16) | (Binary >> 11);
return Binary;
}
case ARM::fixup_t2_pcrel_10:
case ARM::fixup_arm_pcrel_10: {
// Offset by 8 just as above.
Value = Value - 8;
@ -127,6 +128,16 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
Value >>= 2;
assert ((Value < 256) && "Out of range pc-relative fixup value!");
Value |= isAdd << 23;
// Same addressing mode as fixup_arm_pcrel_10, but with the bytes reordered.
if (Kind == ARM::fixup_t2_pcrel_10) {
uint64_t swapped = (Value & 0x00FF0000) >> 16;
swapped |= (Value & 0xFF000000) >> 16;
swapped |= (Value & 0x000000FF) << 16;
swapped |= (Value & 0x0000FF00) << 16;
return swapped;
}
return Value;
}
}
@ -218,6 +229,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
case ARM::fixup_arm_adr_pcrel_12:
case ARM::fixup_arm_branch:
return 3;
case ARM::fixup_t2_pcrel_10:
case ARM::fixup_arm_thumb_bl:
return 4;
}

5
llvm/lib/Target/ARM/ARMFixupKinds.h
View File

@ -19,9 +19,12 @@ enum Fixups {
// addresses
fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
// fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
// used in VFP and Thumb2 instructions where the lower 2 bits are not encoded
// used in VFP instructions where the lower 2 bits are not encoded
// (so it's encoded as an 8-bit immediate).
fixup_arm_pcrel_10,
// fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
// the byteswapped encoding of Thumb2 instructions.
fixup_t2_pcrel_10,
// fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
// instruction.
fixup_arm_adr_pcrel_12,

8
llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -48,6 +48,7 @@ public:
// name off bits flags
{ "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
@ -737,7 +738,12 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
MCFixupKind Kind;
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
if (Subtarget.isThumb2())
Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
else
Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
++MCNumCPRelocations;