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[mips][msa] Remove copy_u.d and move copy_u.w to MSA64. 

Summary:
The forwards compatibility strategy employed by MIPS is to consider registers
to be infinitely sign-extended. Then on ISA's with a wider register, the result
of existing instructions are sign-extended to register width and zero-extended
counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this
strategy and we have therefore corrected the MSA specs to fix this.

We still keep track of sign/zero-extension during legalization but we now
match copy_s.[wd] where required.

No change required to clang since __builtin_msa_copy_u_[wd] will map to
copy_s.[wd] where appropriate for the target.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13472

llvm-svn: 250887
This commit is contained in:
Daniel Sanders 2015-10-21 09:58:54 +00:00
parent 55232f0948
commit 0f596814e9
8 changed files with 51 additions and 48 deletions
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1
llvm/lib/Target/Mips/MipsDSPInstrInfo.td
View File

@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
// ImmLeaf
def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;

6
llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -178,6 +178,8 @@ def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
AssemblerPredicate<"!FeatureGP64Bit">;
def HasMips64 : Predicate<"Subtarget->hasMips64()">,
AssemblerPredicate<"FeatureMips64">;
def NotMips64 : Predicate<"!Subtarget->hasMips64()">,
AssemblerPredicate<"!FeatureMips64">;
def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
AssemblerPredicate<"FeatureMips64r2">;
def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
@ -310,6 +312,10 @@ class ASE_MSA {
list<Predicate> InsnPredicates = [HasMSA];
}
class ASE_MSA_NOT_MSA64 {
list<Predicate> InsnPredicates = [HasMSA, NotMips64];
}
class ASE_MSA64 {
list<Predicate> InsnPredicates = [HasMSA, HasMips64];
}

30
llvm/lib/Target/Mips/MipsMSAInstrInfo.td
View File

@ -63,6 +63,8 @@ def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
def immZExt6Ptr : ImmLeaf<iPTR, [{return isUInt<6>(Imm);}]>;
@ -639,7 +641,6 @@ class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
class COPY_U_D_ENC : MSA_ELM_COPY_D_FMT<0b0011, 0b011001>;
class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
@ -1934,8 +1935,6 @@ class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
GPR32Opnd, MSA128HOpnd>;
class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
GPR32Opnd, MSA128WOpnd>;
class COPY_U_D_DESC : MSA_COPY_DESC_BASE<"copy_u.d", vextract_zext_i64, v2i64,
GPR64Opnd, MSA128DOpnd>;
class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
MSA128W>;
@ -2995,8 +2994,7 @@ def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC, ASE_MSA64;
def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64;
def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
@ -3787,6 +3785,28 @@ def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
MSA128B, NoItinerary>;
// Vector extraction with fixed index.
//
// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
// COPY_U_W, even for the zero-extended case. This is because our forward
// compatibility strategy is to consider registers to be infinitely
// sign-extended so that a MIPS64 can execute MIPS32 code without getting
// different register values.
def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx),
(COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx),
(COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than
// COPY_U_D, even for the zero-extended case. This is because our forward
// compatibility strategy is to consider registers to be infinitely
// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64
// code without getting different register values.
def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx),
(COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx),
(COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
// Vector extraction with variable index
def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
(SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,

5
llvm/test/CodeGen/Mips/msa/elm_copy.ll
View File

@ -170,7 +170,8 @@ declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind
; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1)
; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_ARG1)
; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
; MIPS-ANY-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1]
; MIPS64-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES)
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_RES)
; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
@ -196,7 +197,7 @@ declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind
; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
; MIPS64-DAG: copy_u.d [[RD:\$[0-9]+]], [[WS]][1]
; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1]
; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES)
; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_RES)
; MIPS32-DAG: sw [[RD1]], 0([[RES]])

1
llvm/test/MC/Disassembler/Mips/msa/test_elm.txt
View File

@ -5,7 +5,6 @@
0x78 0xb1 0x2d 0x99 # CHECK: copy_s.w $22, $w5[1]
0x78 0xc4 0xa5 0x99 # CHECK: copy_u.b $22, $w20[4]
0x78 0xe0 0x25 0x19 # CHECK: copy_u.h $20, $w4[0]
0x78 0xf2 0x6f 0x99 # CHECK: copy_u.w $fp, $w13[2]
0x78 0x04 0xe8 0x19 # CHECK: sldi.b $w0, $w29[4]
0x78 0x20 0x8a 0x19 # CHECK: sldi.h $w8, $w17[0]
0x78 0x32 0xdd 0x19 # CHECK: sldi.w $w20, $w27[2]

5
llvm/test/MC/Disassembler/Mips/msa/test_elm_msa64.txt
View File

@ -1,6 +1,3 @@
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s
# CHECK: copy_s.d $19, $w31[0]
0x78 0xb8 0xfc 0xd9
# CHECK: copy_u.d $18, $w29[1]
0x78 0xf9 0xec 0x99
0x78 0xb8 0xfc 0xd9 # CHECK: copy_s.d $19, $w31[0]

45
llvm/test/MC/Mips/msa/test_elm.s
View File

@ -1,33 +1,16 @@
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: copy_s.b $13, $w8[2] # encoding: [0x78,0x82,0x43,0x59]
# CHECK: copy_s.h $1, $w25[0] # encoding: [0x78,0xa0,0xc8,0x59]
# CHECK: copy_s.w $22, $w5[1] # encoding: [0x78,0xb1,0x2d,0x99]
# CHECK: copy_u.b $22, $w20[4] # encoding: [0x78,0xc4,0xa5,0x99]
# CHECK: copy_u.h $20, $w4[0] # encoding: [0x78,0xe0,0x25,0x19]
# CHECK: copy_u.w $fp, $w13[2] # encoding: [0x78,0xf2,0x6f,0x99]
# CHECK: sldi.b $w0, $w29[4] # encoding: [0x78,0x04,0xe8,0x19]
# CHECK: sldi.h $w8, $w17[0] # encoding: [0x78,0x20,0x8a,0x19]
# CHECK: sldi.w $w20, $w27[2] # encoding: [0x78,0x32,0xdd,0x19]
# CHECK: sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
# CHECK: splati.b $w25, $w3[2] # encoding: [0x78,0x42,0x1e,0x59]
# CHECK: splati.h $w24, $w28[1] # encoding: [0x78,0x61,0xe6,0x19]
# CHECK: splati.w $w13, $w18[0] # encoding: [0x78,0x70,0x93,0x59]
# CHECK: splati.d $w28, $w1[0] # encoding: [0x78,0x78,0x0f,0x19]
# CHECK: move.v $w23, $w24 # encoding: [0x78,0xbe,0xc5,0xd9]
copy_s.b $13, $w8[2]
copy_s.h $1, $w25[0]
copy_s.w $22, $w5[1]
copy_u.b $22, $w20[4]
copy_u.h $20, $w4[0]
copy_u.w $30, $w13[2]
sldi.b $w0, $w29[4]
sldi.h $w8, $w17[0]
sldi.w $w20, $w27[2]
sldi.d $w4, $w12[0]
splati.b $w25, $w3[2]
splati.h $w24, $w28[1]
splati.w $w13, $w18[0]
splati.d $w28, $w1[0]
move.v $w23, $w24
copy_s.b $13, $w8[2] # CHECK: copy_s.b $13, $w8[2] # encoding: [0x78,0x82,0x43,0x59]
copy_s.h $1, $w25[0] # CHECK: copy_s.h $1, $w25[0] # encoding: [0x78,0xa0,0xc8,0x59]
copy_s.w $22, $w5[1] # CHECK: copy_s.w $22, $w5[1] # encoding: [0x78,0xb1,0x2d,0x99]
copy_u.b $22, $w20[4] # CHECK: copy_u.b $22, $w20[4] # encoding: [0x78,0xc4,0xa5,0x99]
copy_u.h $20, $w4[0] # CHECK: copy_u.h $20, $w4[0] # encoding: [0x78,0xe0,0x25,0x19]
sldi.b $w0, $w29[4] # CHECK: sldi.b $w0, $w29[4] # encoding: [0x78,0x04,0xe8,0x19]
sldi.h $w8, $w17[0] # CHECK: sldi.h $w8, $w17[0] # encoding: [0x78,0x20,0x8a,0x19]
sldi.w $w20, $w27[2] # CHECK: sldi.w $w20, $w27[2] # encoding: [0x78,0x32,0xdd,0x19]
sldi.d $w4, $w12[0] # CHECK: sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
splati.b $w25, $w3[2] # CHECK: splati.b $w25, $w3[2] # encoding: [0x78,0x42,0x1e,0x59]
splati.h $w24, $w28[1] # CHECK: splati.h $w24, $w28[1] # encoding: [0x78,0x61,0xe6,0x19]
splati.w $w13, $w18[0] # CHECK: splati.w $w13, $w18[0] # encoding: [0x78,0x70,0x93,0x59]
splati.d $w28, $w1[0] # CHECK: splati.d $w28, $w1[0] # encoding: [0x78,0x78,0x0f,0x19]
move.v $w23, $w24 # CHECK: move.v $w23, $w24 # encoding: [0x78,0xbe,0xc5,0xd9]

6
llvm/test/MC/Mips/msa/test_elm_msa64.s
View File

@ -1,7 +1,3 @@
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: copy_s.d $19, $w31[0] # encoding: [0x78,0xb8,0xfc,0xd9]
# CHECK: copy_u.d $18, $w29[1] # encoding: [0x78,0xf9,0xec,0x99]
copy_s.d $19, $w31[0]
copy_u.d $18, $w29[1]
copy_s.d $19, $w31[0] # CHECK: copy_s.d $19, $w31[0] # encoding: [0x78,0xb8,0xfc,0xd9]