forked from OSchip/llvm-project
parent
c3c1441bda
commit
0f2c1cf429
|
@ -3984,8 +3984,6 @@ SDValue TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
|
||||||
unsigned Stride = SrcEltVT.getSizeInBits() / 8;
|
unsigned Stride = SrcEltVT.getSizeInBits() / 8;
|
||||||
assert(SrcEltVT.isByteSized());
|
assert(SrcEltVT.isByteSized());
|
||||||
|
|
||||||
EVT PtrVT = BasePTR.getValueType();
|
|
||||||
|
|
||||||
SmallVector<SDValue, 8> Vals;
|
SmallVector<SDValue, 8> Vals;
|
||||||
SmallVector<SDValue, 8> LoadChains;
|
SmallVector<SDValue, 8> LoadChains;
|
||||||
|
|
||||||
|
@ -3996,8 +3994,7 @@ SDValue TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
|
||||||
SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride),
|
SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride),
|
||||||
LD->getMemOperand()->getFlags(), LD->getAAInfo());
|
LD->getMemOperand()->getFlags(), LD->getAAInfo());
|
||||||
|
|
||||||
BasePTR = DAG.getNode(ISD::ADD, SL, PtrVT, BasePTR,
|
BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, Stride);
|
||||||
DAG.getConstant(Stride, SL, PtrVT));
|
|
||||||
|
|
||||||
Vals.push_back(ScalarLoad.getValue(0));
|
Vals.push_back(ScalarLoad.getValue(0));
|
||||||
LoadChains.push_back(ScalarLoad.getValue(1));
|
LoadChains.push_back(ScalarLoad.getValue(1));
|
||||||
|
|
Loading…
Reference in New Issue