From 0f2158b35fef76fa39c6b472e3e2be0b583d2224 Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Sat, 27 Jun 2009 12:59:03 +0000 Subject: [PATCH] Simplify a bit llvm-svn: 74385 --- llvm/lib/Target/ARM/ARMInstrInfo.cpp | 8 +-- llvm/lib/Target/ARM/ARMRegisterInfo.cpp | 60 +++++++++-------------- llvm/lib/Target/ARM/ARMRegisterInfo.h | 23 ++++++--- llvm/lib/Target/ARM/ThumbInstrInfo.cpp | 8 +-- llvm/lib/Target/ARM/ThumbRegisterInfo.cpp | 46 +++++++++-------- llvm/lib/Target/ARM/ThumbRegisterInfo.h | 5 -- 6 files changed, 70 insertions(+), 80 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp index 034b697ab58a..5d77e9913681 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp @@ -138,9 +138,11 @@ void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB, const MachineInstr *Orig) const { DebugLoc dl = Orig->getDebugLoc(); if (Orig->getOpcode() == ARM::MOVi2pieces) { - RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(), - Orig->getOperand(2).getImm(), - Orig->getOperand(3).getReg(), this, dl); + RI.emitLoadConstPool(MBB, I, this, dl, + DestReg, + Orig->getOperand(1).getImm(), + (ARMCC::CondCodes)Orig->getOperand(2).getImm(), + Orig->getOperand(3).getReg()); return; } diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp index a58e8ec0e0a0..c898af9b4963 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp @@ -174,10 +174,10 @@ const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { /// specified immediate. void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, + const TargetInstrInfo *TII, DebugLoc dl, unsigned DestReg, int Val, - unsigned Pred, unsigned PredReg, - const TargetInstrInfo *TII, - DebugLoc dl) const { + ARMCC::CondCodes Pred, + unsigned PredReg) const { MachineFunction &MF = *MBB.getParent(); MachineConstantPool *ConstantPool = MF.getConstantPool(); Constant *C = ConstantInt::get(Type::Int32Ty, Val); @@ -188,19 +188,6 @@ void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } -/// isLowRegister - Returns true if the register is low register r0-r7. -/// -bool ARMBaseRegisterInfo::isLowRegister(unsigned Reg) const { - using namespace ARM; - switch (Reg) { - case R0: case R1: case R2: case R3: - case R4: case R5: case R6: case R7: - return true; - default: - return false; - } -} - const unsigned* ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { static const unsigned CalleeSavedRegs[] = { @@ -558,10 +545,11 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB, } } -void ARMRegisterInfo:: +static void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, - const TargetInstrInfo &TII, DebugLoc dl) const { + const TargetInstrInfo &TII, DebugLoc dl, + int NumBytes, + ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, Pred, PredReg, TII, dl); } @@ -589,12 +577,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. unsigned PredReg = Old->getOperand(2).getReg(); - emitSPUpdate(MBB, I, -Amount, Pred, PredReg, TII, dl); + emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg); } else { // Note: PredReg is operand 3 for ADJCALLSTACKUP. unsigned PredReg = Old->getOperand(3).getReg(); assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); - emitSPUpdate(MBB, I, Amount, Pred, PredReg, TII, dl); + emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg); } } } @@ -926,7 +914,8 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { unsigned Reg = UnspilledCS1GPRs[i]; // Don't spiil high register if the function is thumb - if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { + if (!AFI->isThumbFunction() || + isARMLowRegister(Reg) || Reg == ARM::LR) { MF.getRegInfo().setPhysRegUsed(Reg); AFI->setCSRegisterIsSpilled(Reg); if (!isReservedReg(MF, Reg)) @@ -1066,11 +1055,11 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { int FramePtrSpillFI = 0; if (VARegSaveSize) - emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize); if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes); return; } @@ -1109,7 +1098,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { } // Build the new SUBri to adjust SP for integer callee-save spill area 1. - emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size); movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); // Darwin ABI requires FP to point to the stack slot that contains the @@ -1122,11 +1111,11 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { } // Build the new SUBri to adjust SP for integer callee-save spill area 2. - emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size); // Build the new SUBri to adjust SP for FP callee-save spill area. movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); - emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize); // Determine starting offsets of spill areas. unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); @@ -1141,7 +1130,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { if (NumBytes) { // Insert it after all the callee-save spills. movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); - emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes); } if (STI.isTargetELF() && hasFP(MF)) { @@ -1181,7 +1170,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, NumBytes); } else { // Unwind MBBI to point to first LDR / FLDD. const unsigned *CSRegs = getCalleeSavedRegs(); @@ -1217,27 +1206,24 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); } } else if (NumBytes) { - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, NumBytes); } // Move SP to start of integer callee save spill area 2. movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); - emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, - TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize()); // Move SP to start of integer callee save spill area 1. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); - emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, - TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size()); // Move SP to SP upon entry to the function. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); - emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, - TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size()); } if (VARegSaveSize) - emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize); } diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.h b/llvm/lib/Target/ARM/ARMRegisterInfo.h index 1154c0542b33..7fe075a65ee8 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.h +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.h @@ -31,6 +31,19 @@ namespace ARMRI { }; } +/// isARMLowRegister - Returns true if the register is low register r0-r7. +/// +static inline bool isARMLowRegister(unsigned Reg) { + using namespace ARM; + switch (Reg) { + case R0: case R1: case R2: case R3: + case R4: case R5: case R6: case R7: + return true; + default: + return false; + } +} + struct ARMBaseRegisterInfo : public ARMGenRegisterInfo { protected: const TargetInstrInfo &TII; @@ -103,10 +116,10 @@ public: /// specified immediate. void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, + const TargetInstrInfo *TII, DebugLoc dl, unsigned DestReg, int Val, - unsigned Pred, unsigned PredReg, - const TargetInstrInfo *TII, - DebugLoc dl) const; + ARMCC::CondCodes Pred = ARMCC::AL, + unsigned PredReg = 0) const; /// Code Generation virtual methods... bool isReservedReg(const MachineFunction &MF, unsigned Reg) const; @@ -124,10 +137,6 @@ public: void emitPrologue(MachineFunction &MF) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, - const TargetInstrInfo &TII, DebugLoc dl) const; }; } // end namespace llvm diff --git a/llvm/lib/Target/ARM/ThumbInstrInfo.cpp b/llvm/lib/Target/ARM/ThumbInstrInfo.cpp index d9a499dacd15..803e39c962af 100644 --- a/llvm/lib/Target/ARM/ThumbInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ThumbInstrInfo.cpp @@ -129,12 +129,12 @@ canFoldMemoryOperand(const MachineInstr *MI, case ARM::tMOVhir2hir: { if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); - if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg)) + if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg)) // tSpill cannot take a high register operand. return false; } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); - if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg)) + if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg)) // tRestore cannot target a high register operand. return false; } @@ -288,7 +288,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg)) + if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg)) // tSpill cannot take a high register operand. break; NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) @@ -296,7 +296,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, .addFrameIndex(FI).addImm(0); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); - if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg)) + if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg)) // tRestore cannot target a high register operand. break; bool isDead = MI->getOperand(0).isDead(); diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp index 40221d9cf7d2..513126f57128 100644 --- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp @@ -47,7 +47,6 @@ ThumbRegisterInfo::ThumbRegisterInfo(const TargetInstrInfo &tii, void ThumbRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Val, - unsigned Pred, unsigned PredReg, const TargetInstrInfo *TII, DebugLoc dl) const { MachineFunction &MF = *MBB.getParent(); @@ -61,7 +60,7 @@ void ThumbRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, const TargetRegisterClass* ThumbRegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const { - if (isLowRegister(Reg)) + if (isARMLowRegister(Reg)) return ARM::tGPRRegisterClass; switch (Reg) { default: @@ -104,8 +103,8 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, const TargetInstrInfo &TII, const ThumbRegisterInfo& MRI, DebugLoc dl) { - bool isHigh = !MRI.isLowRegister(DestReg) || - (BaseReg != 0 && !MRI.isLowRegister(BaseReg)); + bool isHigh = !isARMLowRegister(DestReg) || + (BaseReg != 0 && !isARMLowRegister(BaseReg)); bool isSub = false; // Subtract doesn't have high register version. Load the negative value // if either base or dest register is a high register. Also, if do not @@ -130,7 +129,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, RegState::Kill); } else - MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII, dl); + MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, &TII, dl); // Emit add / sub. int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); @@ -229,7 +228,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, } if (DstNotEqBase) { - if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) { + if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) { // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) unsigned Chunk = (1 << 3) - 1; unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; @@ -277,12 +276,13 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, .addImm(((unsigned)NumBytes) & 3); } -void ThumbRegisterInfo:: -emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, - const TargetInstrInfo &TII, DebugLoc dl) const { +static void emitSPUpdate(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + const TargetInstrInfo &TII, DebugLoc dl, + const ThumbRegisterInfo &MRI, + int NumBytes) { emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, - *this, dl); + MRI, dl); } void ThumbRegisterInfo:: @@ -305,12 +305,10 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, // Replace the pseudo instruction with a new instruction... unsigned Opc = Old->getOpcode(); if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { - // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. - emitSPUpdate(MBB, I, -Amount, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, I, TII, dl, *this, -Amount); } else { - // Note: PredReg is operand 3 for ADJCALLSTACKUP. assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); - emitSPUpdate(MBB, I, Amount, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, I, TII, dl, *this, Amount); } } } @@ -506,7 +504,7 @@ void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, dl); + emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl); UseRR = true; } } else @@ -544,7 +542,7 @@ void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, dl); + emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl); UseRR = true; } } else @@ -598,11 +596,11 @@ void ThumbRegisterInfo::emitPrologue(MachineFunction &MF) const { int FramePtrSpillFI = 0; if (VARegSaveSize) - emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize); if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes); return; } @@ -666,7 +664,7 @@ void ThumbRegisterInfo::emitPrologue(MachineFunction &MF) const { NumBytes = DPRCSOffset; if (NumBytes) { // Insert it after all the callee-save spills. - emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes); } if (STI.isTargetELF() && hasFP(MF)) { @@ -706,7 +704,7 @@ void ThumbRegisterInfo::emitEpilogue(MachineFunction &MF, if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes); } else { // Unwind MBBI to point to first LDR / FLDD. const unsigned *CSRegs = getCalleeSavedRegs(); @@ -738,9 +736,9 @@ void ThumbRegisterInfo::emitEpilogue(MachineFunction &MF, &MBB.front() != MBBI && prior(MBBI)->getOpcode() == ARM::tPOP) { MachineBasicBlock::iterator PMBBI = prior(MBBI); - emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes); } else - emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes); } } @@ -749,7 +747,7 @@ void ThumbRegisterInfo::emitEpilogue(MachineFunction &MF, // FIXME: Verify this is still ok when R3 is no longer being reserved. BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3); - emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, TII, dl); + emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize); BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); MBB.erase(MBBI); diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.h b/llvm/lib/Target/ARM/ThumbRegisterInfo.h index b1adc3185831..82ca337a8101 100644 --- a/llvm/lib/Target/ARM/ThumbRegisterInfo.h +++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.h @@ -32,7 +32,6 @@ public: void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Val, - unsigned Pred, unsigned PredReg, const TargetInstrInfo *TII, DebugLoc dl) const; @@ -55,10 +54,6 @@ public: void emitPrologue(MachineFunction &MF) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, - const TargetInstrInfo &TII, DebugLoc dl) const; }; }