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[mips] Range check simm5. 

Summary:
We can't check the error message for this one because there's another lw/sw
available that covers a larger range. We therefore check the transition
between the two sizes.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18144

llvm-svn: 264054
This commit is contained in:
Daniel Sanders 2016-03-22 14:29:53 +00:00
parent 946dee3b5b
commit 0f17d0da4a
4 changed files with 10 additions and 3 deletions
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3
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -3729,6 +3729,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_UImm5_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 5-bit unsigned immediate");
case Match_SImm5_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 5-bit signed immediate");
case Match_UImm5_1:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range 1 .. 32");

6
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -507,8 +507,10 @@ def ConstantUImm5Plus1AsmOperandClass
5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>;
def ConstantUImm5AsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus1AsmOperandClass]>;
def ConstantSImm5AsmOperandClass
: ConstantSImmAsmOperandClass<5, [ConstantUImm5AsmOperandClass]>;
def ConstantUImm4AsmOperandClass
: ConstantUImmAsmOperandClass<4, [ConstantUImm5AsmOperandClass]>;
: ConstantUImmAsmOperandClass<4, [ConstantSImm5AsmOperandClass]>;
def ConstantSImm4AsmOperandClass
: ConstantSImmAsmOperandClass<4, [ConstantUImm4AsmOperandClass]>;
def ConstantUImm3AsmOperandClass
@ -724,7 +726,7 @@ foreach I = {1, 2, 3, 4, 5, 6, 8} in
}
// Signed operands
foreach I = {4} in
foreach I = {4, 5} in
def simm # I : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffset<" # I # ">";
let ParserMatchClass =

1
llvm/lib/Target/Mips/MipsMSAInstrInfo.td
View File

@ -70,7 +70,6 @@ def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
// Operands
def simm5 : Operand<i32>;
def vsplat_simm5 : Operand<vAny>;

3
llvm/test/MC/Mips/micromips32r6/valid.s
View File

@ -80,6 +80,7 @@
sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90]
subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
sw $4, 124($sp) # CHECK: sw $4, 124($sp) # encoding: [0xc8,0x9f]
sw $4, 128($sp) # CHECK: sw $4, 128($sp) # encoding: [0xf8,0x9d,0x00,0x80]
sw16 $4, 4($17) # CHECK: sw16 $4, 4($17) # encoding: [0xea,0x11]
sw16 $0, 4($17) # CHECK: sw16 $zero, 4($17) # encoding: [0xe8,0x11]
swm $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
@ -189,6 +190,8 @@
rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66]
lw $3, 124($sp) # CHECK: lw $3, 124($sp) # encoding: [0x48,0x7f]
lw $3, 128($sp) # CHECK: lw $3, 128($sp) # encoding: [0xfc,0x7d,0x00,0x80]
lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12]
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]