forked from OSchip/llvm-project
[AArch64][GlobalISel] Introduce a new post-isel optimization pass.
There are two optimizations here: 1. Consider the following code: FCMPSrr %0, %1, implicit-def $nzcv %sel1:gpr32 = CSELWr %_, %_, 12, implicit $nzcv %sub:gpr32 = SUBSWrr %_, %_, implicit-def $nzcv FCMPSrr %0, %1, implicit-def $nzcv %sel2:gpr32 = CSELWr %_, %_, 12, implicit $nzcv This kind of code where we have 2 FCMPs each feeding a CSEL can happen when we have a single IR fcmp being used by two selects. During selection, to ensure that there can be no clobbering of nzcv between the fcmp and the csel, we have to generate an fcmp immediately before each csel is selected. However, often we can essentially CSE these together later in MachineCSE. This doesn't work though if there are unrelated flag-setting instructions in between the two FCMPs. In this case, the SUBS defines NZCV but it doesn't have any users, being overwritten by the second FCMP. Our solution here is to try to convert flag setting operations between a interval of identical FCMPs, so that CSE will be able to eliminate one. 2. SelectionDAG imported patterns for arithmetic ops currently select the flag-setting ops for CSE reasons, and add the implicit-def $nzcv operand to those instructions. However if those impdef operands are not marked as dead, the peephole optimizations are not able to optimize them into non-flag setting variants. The optimization here is to find these dead imp-defs and mark them as such. This pass is only enabled when optimizations are enabled. Differential Revision: https://reviews.llvm.org/D89415
This commit is contained in:
Amara Emerson
parent
bf44d3689a
commit
0f0fd383b4
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@ -61,6 +61,7 @@ createAArch64InstructionSelector(const AArch64TargetMachine &,
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FunctionPass *createAArch64PreLegalizerCombiner(bool IsOptNone);
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FunctionPass *createAArch64PostLegalizerCombiner(bool IsOptNone);
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FunctionPass *createAArch64PostLegalizerLowering();
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FunctionPass *createAArch64PostSelectOptimize();
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FunctionPass *createAArch64StackTaggingPass(bool IsOptNone);
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FunctionPass *createAArch64StackTaggingPreRAPass();
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@ -82,6 +83,7 @@ void initializeAArch64SIMDInstrOptPass(PassRegistry&);
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void initializeAArch64PreLegalizerCombinerPass(PassRegistry&);
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void initializeAArch64PostLegalizerCombinerPass(PassRegistry &);
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void initializeAArch64PostLegalizerLoweringPass(PassRegistry &);
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void initializeAArch64PostSelectOptimizePass(PassRegistry &);
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void initializeAArch64PromoteConstantPass(PassRegistry&);
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void initializeAArch64RedundantCopyEliminationPass(PassRegistry&);
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void initializeAArch64StorePairSuppressPass(PassRegistry&);
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@ -185,6 +185,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
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initializeAArch64PreLegalizerCombinerPass(*PR);
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initializeAArch64PostLegalizerCombinerPass(*PR);
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initializeAArch64PostLegalizerLoweringPass(*PR);
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initializeAArch64PostSelectOptimizePass(*PR);
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initializeAArch64PromoteConstantPass(*PR);
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initializeAArch64RedundantCopyEliminationPass(*PR);
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initializeAArch64StorePairSuppressPass(*PR);
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@ -577,6 +578,8 @@ void AArch64PassConfig::addPreGlobalInstructionSelect() {
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bool AArch64PassConfig::addGlobalInstructionSelect() {
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addPass(new InstructionSelect());
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createAArch64PostSelectOptimize());
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return false;
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}
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@ -32,6 +32,7 @@ add_llvm_target(AArch64CodeGen
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GISel/AArch64PreLegalizerCombiner.cpp
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GISel/AArch64PostLegalizerCombiner.cpp
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GISel/AArch64PostLegalizerLowering.cpp
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GISel/AArch64PostSelectOptimize.cpp
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GISel/AArch64RegisterBankInfo.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp
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@ -0,0 +1,187 @@
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//=== AArch64PostSelectOptimize.cpp ---------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does post-instruction-selection optimizations in the GlobalISel
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// pipeline, before the rest of codegen runs.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "aarch64-post-select-optimize"
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using namespace llvm;
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namespace {
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class AArch64PostSelectOptimize : public MachineFunctionPass {
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public:
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static char ID;
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AArch64PostSelectOptimize();
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StringRef getPassName() const override {
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return "AArch64 Post Select Optimizer";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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bool optimizeNZCVDefs(MachineBasicBlock &MBB);
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};
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} // end anonymous namespace
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void AArch64PostSelectOptimize::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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AArch64PostSelectOptimize::AArch64PostSelectOptimize()
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: MachineFunctionPass(ID) {
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initializeAArch64PostSelectOptimizePass(*PassRegistry::getPassRegistry());
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}
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unsigned getNonFlagSettingVariant(unsigned Opc) {
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switch (Opc) {
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default:
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return 0;
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case AArch64::SUBSXrr:
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return AArch64::SUBXrr;
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case AArch64::SUBSWrr:
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return AArch64::SUBWrr;
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case AArch64::SUBSXrs:
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return AArch64::SUBXrs;
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case AArch64::SUBSXri:
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return AArch64::SUBXri;
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case AArch64::SUBSWri:
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return AArch64::SUBWri;
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}
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}
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bool AArch64PostSelectOptimize::optimizeNZCVDefs(MachineBasicBlock &MBB) {
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// Consider the following code:
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// FCMPSrr %0, %1, implicit-def $nzcv
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// %sel1:gpr32 = CSELWr %_, %_, 12, implicit $nzcv
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// %sub:gpr32 = SUBSWrr %_, %_, implicit-def $nzcv
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// FCMPSrr %0, %1, implicit-def $nzcv
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// %sel2:gpr32 = CSELWr %_, %_, 12, implicit $nzcv
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// This kind of code where we have 2 FCMPs each feeding a CSEL can happen
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// when we have a single IR fcmp being used by two selects. During selection,
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// to ensure that there can be no clobbering of nzcv between the fcmp and the
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// csel, we have to generate an fcmp immediately before each csel is
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// selected.
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// However, often we can essentially CSE these together later in MachineCSE.
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// This doesn't work though if there are unrelated flag-setting instructions
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// in between the two FCMPs. In this case, the SUBS defines NZCV
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// but it doesn't have any users, being overwritten by the second FCMP.
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//
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// Our solution here is to try to convert flag setting operations between
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// a interval of identical FCMPs, so that CSE will be able to eliminate one.
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bool Changed = false;
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const auto *TII = MBB.getParent()->getSubtarget().getInstrInfo();
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// The first step is to find the first and last FCMPs. If we have found
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// at least two, then set the limit of the bottom-up walk to the first FCMP
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// found since we're only interested in dealing with instructions between
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// them.
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MachineInstr *FirstCmp = nullptr, *LastCmp = nullptr;
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for (auto &MI : instructionsWithoutDebug(MBB.begin(), MBB.end())) {
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if (MI.getOpcode() == AArch64::FCMPSrr ||
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MI.getOpcode() == AArch64::FCMPDrr) {
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if (!FirstCmp)
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FirstCmp = &MI;
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else
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LastCmp = &MI;
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}
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}
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// In addition to converting flag-setting ops in fcmp ranges into non-flag
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// setting ops, across the whole basic block we also detect when nzcv
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// implicit-defs are dead, and mark them as dead. Peephole optimizations need
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// this information later.
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LiveRegUnits LRU(*MBB.getParent()->getSubtarget().getRegisterInfo());
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LRU.addLiveOuts(MBB);
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bool NZCVDead = LRU.available(AArch64::NZCV);
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bool InsideCmpRange = false;
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for (auto &II : instructionsWithoutDebug(MBB.rbegin(), MBB.rend())) {
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LRU.stepBackward(II);
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if (LastCmp) { // There's a range present in this block.
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// If we're inside an fcmp range, look for begin instruction.
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if (InsideCmpRange && &II == FirstCmp)
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InsideCmpRange = false;
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else if (&II == LastCmp)
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InsideCmpRange = true;
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}
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// Did this instruction define NZCV?
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bool NZCVDeadAtCurrInstr = LRU.available(AArch64::NZCV);
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if (NZCVDead && NZCVDeadAtCurrInstr && II.definesRegister(AArch64::NZCV)) {
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// If we have a def and NZCV is dead, then we may convert this op.
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unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode());
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int DeadNZCVIdx = II.findRegisterDefOperandIdx(AArch64::NZCV);
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if (DeadNZCVIdx != -1) {
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// If we're inside an fcmp range, then convert flag setting ops.
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if (InsideCmpRange && NewOpc) {
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LLVM_DEBUG(dbgs() << "Post-select optimizer: converting flag-setting "
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"op in fcmp range: "
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<< II);
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II.setDesc(TII->get(NewOpc));
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II.RemoveOperand(DeadNZCVIdx);
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Changed |= true;
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} else {
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// Otherwise, we just set the nzcv imp-def operand to be dead, so the
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// peephole optimizations can optimize them further.
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II.getOperand(DeadNZCVIdx).setIsDead();
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}
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}
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}
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NZCVDead = NZCVDeadAtCurrInstr;
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}
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return Changed;
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}
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bool AArch64PostSelectOptimize::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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assert(MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::Selected) &&
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"Expected a selected MF");
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bool Changed = false;
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for (auto &BB : MF)
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Changed |= optimizeNZCVDefs(BB);
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return true;
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}
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char AArch64PostSelectOptimize::ID = 0;
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INITIALIZE_PASS_BEGIN(AArch64PostSelectOptimize, DEBUG_TYPE,
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"Optimize AArch64 selected instructions",
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false, false)
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INITIALIZE_PASS_END(AArch64PostSelectOptimize, DEBUG_TYPE,
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"Optimize AArch64 selected instructions", false,
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false)
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namespace llvm {
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FunctionPass *createAArch64PostSelectOptimize() {
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return new AArch64PostSelectOptimize();
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}
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} // end namespace llvm
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@ -67,6 +67,7 @@
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; VERIFY-O0-NEXT: Verify generated machine code
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; ENABLED-NEXT: Analysis for ComputingKnownBits
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; ENABLED-NEXT: InstructionSelect
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; ENABLED-O1-NEXT: AArch64 Post Select Optimizer
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED-NEXT: ResetMachineFunction
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@ -0,0 +1,181 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_fcmp_dead_cc
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w1, $x0, $s0, $s1
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; CHECK-LABEL: name: test_fcmp_dead_cc
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; CHECK: liveins: $w1, $x0, $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
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; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr64 = COPY $x0
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%2:gpr32 = COPY $w1
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%3:fpr32 = COPY $s0
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%4:fpr32 = COPY $s1
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%26:gpr32 = COPY $wzr
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FCMPSrr %3, %4, implicit-def $nzcv
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%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
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FCMPSrr %3, %4, implicit-def $nzcv
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%14:gpr32common = UBFMWri %12, 1, 31
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%60:gpr32 = MOVi32imm 1
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%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
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$w0 = COPY %16
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RET_ReallyLR implicit $w0
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...
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---
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name: test_fcmp_64_dead_cc
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w1, $x0, $d0, $d1
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; CHECK-LABEL: name: test_fcmp_64_dead_cc
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; CHECK: liveins: $w1, $x0, $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
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; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
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; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr64 = COPY $x0
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%2:gpr32 = COPY $w1
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%3:fpr64 = COPY $d0
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%4:fpr64 = COPY $d1
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%26:gpr32 = COPY $wzr
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FCMPDrr %3, %4, implicit-def $nzcv
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%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
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FCMPDrr %3, %4, implicit-def $nzcv
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%14:gpr32common = UBFMWri %12, 1, 31
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%60:gpr32 = MOVi32imm 1
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%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
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$w0 = COPY %16
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RET_ReallyLR implicit $w0
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...
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---
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name: test_fcmp_dead_cc_3_fcmps
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w1, $x0, $s0, $s1
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; CHECK-LABEL: name: test_fcmp_dead_cc_3_fcmps
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; CHECK: liveins: $w1, $x0, $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
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; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
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; CHECK: [[SUBWrr1:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr1]], 1, 31
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr64 = COPY $x0
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%2:gpr32 = COPY $w1
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%3:fpr32 = COPY $s0
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%4:fpr32 = COPY $s1
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%26:gpr32 = COPY $wzr
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FCMPSrr %3, %4, implicit-def $nzcv
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%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
|
||||
FCMPSrr %3, %4, implicit-def $nzcv
|
||||
%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
|
||||
FCMPSrr %3, %4, implicit-def $nzcv
|
||||
%14:gpr32common = UBFMWri %12, 1, 31
|
||||
%60:gpr32 = MOVi32imm 1
|
||||
%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
|
||||
$w0 = COPY %16
|
||||
RET_ReallyLR implicit $w0
|
||||
|
||||
...
|
||||
---
|
||||
name: test_impdef_made_dead
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: true
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$x0' }
|
||||
- { reg: '$w1' }
|
||||
body: |
|
||||
bb.1:
|
||||
liveins: $w1, $x0, $s0, $s1
|
||||
; Check that any dead imp-defs of NZCV are marked as such.
|
||||
; CHECK-LABEL: name: test_impdef_made_dead
|
||||
; CHECK: liveins: $w1, $x0, $s0, $s1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
|
||||
; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
|
||||
; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY4]], implicit-def dead $nzcv
|
||||
; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
|
||||
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBSWrr]], 1, 31
|
||||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
|
||||
; CHECK: %ret:gpr32 = SUBSWrr [[CSELWr]], [[SUBSWrr]], implicit-def dead $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%1:gpr64 = COPY $x0
|
||||
%2:gpr32 = COPY $w1
|
||||
%3:fpr32 = COPY $s0
|
||||
%4:fpr32 = COPY $s1
|
||||
%26:gpr32 = COPY $wzr
|
||||
%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
|
||||
FCMPSrr %3, %4, implicit-def $nzcv
|
||||
%14:gpr32common = UBFMWri %12, 1, 31
|
||||
%60:gpr32 = MOVi32imm 1
|
||||
%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
|
||||
%ret:gpr32 = SUBSWrr %16, %12, implicit-def $nzcv
|
||||
$w0 = COPY %16
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
; RUN: llc -debugify-and-strip-all-safe -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s
|
||||
; RUN: llc -debugify-and-strip-all-safe -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 -global-isel -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
|
||||
; RUN: llc -debugify-and-strip-all-safe -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 -global-isel -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
|
||||
|
||||
; FALLBACK-NOT: remark
|
||||
|
||||
|
|
@ -8,28 +8,24 @@
|
|||
|
||||
define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
|
||||
; CHECK-LABEL: test_lsl_arith:
|
||||
; GISEL-LABEL: test_lsl_arith:
|
||||
|
||||
%rhs1 = load volatile i32, i32* @var32
|
||||
%shift1 = shl i32 %rhs1, 18
|
||||
%val1 = add i32 %lhs32, %shift1
|
||||
store volatile i32 %val1, i32* @var32
|
||||
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #18
|
||||
; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #18
|
||||
|
||||
%rhs2 = load volatile i32, i32* @var32
|
||||
%shift2 = shl i32 %rhs2, 31
|
||||
%val2 = add i32 %shift2, %lhs32
|
||||
store volatile i32 %val2, i32* @var32
|
||||
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
|
||||
; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
|
||||
|
||||
%rhs3 = load volatile i32, i32* @var32
|
||||
%shift3 = shl i32 %rhs3, 5
|
||||
%val3 = sub i32 %lhs32, %shift3
|
||||
store volatile i32 %val3, i32* @var32
|
||||
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #5
|
||||
; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #5
|
||||
|
||||
; Subtraction is not commutative!
|
||||
%rhs4 = load volatile i32, i32* @var32
|
||||
|
|
@ -37,35 +33,30 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
|
|||
%val4 = sub i32 %shift4, %lhs32
|
||||
store volatile i32 %val4, i32* @var32
|
||||
; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #19
|
||||
; GISEL-NOT: sub{{[s]?}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #19
|
||||
|
||||
%lhs4a = load volatile i32, i32* @var32
|
||||
%shift4a = shl i32 %lhs4a, 15
|
||||
%val4a = sub i32 0, %shift4a
|
||||
store volatile i32 %val4a, i32* @var32
|
||||
; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, lsl #15
|
||||
; GISEL: negs {{w[0-9]+}}, {{w[0-9]+}}, lsl #15
|
||||
|
||||
%rhs5 = load volatile i64, i64* @var64
|
||||
%shift5 = shl i64 %rhs5, 18
|
||||
%val5 = add i64 %lhs64, %shift5
|
||||
store volatile i64 %val5, i64* @var64
|
||||
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #18
|
||||
; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #18
|
||||
|
||||
%rhs6 = load volatile i64, i64* @var64
|
||||
%shift6 = shl i64 %rhs6, 31
|
||||
%val6 = add i64 %shift6, %lhs64
|
||||
store volatile i64 %val6, i64* @var64
|
||||
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #31
|
||||
; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #31
|
||||
|
||||
%rhs7 = load volatile i64, i64* @var64
|
||||
%shift7 = shl i64 %rhs7, 5
|
||||
%val7 = sub i64 %lhs64, %shift7
|
||||
store volatile i64 %val7, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #5
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #5
|
||||
|
||||
; Subtraction is not commutative!
|
||||
%rhs8 = load volatile i64, i64* @var64
|
||||
|
|
@ -73,14 +64,12 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
|
|||
%val8 = sub i64 %shift8, %lhs64
|
||||
store volatile i64 %val8, i64* @var64
|
||||
; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #19
|
||||
; GISEL-NOT: sub{{[s]?}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #19
|
||||
|
||||
%lhs8a = load volatile i64, i64* @var64
|
||||
%shift8a = shl i64 %lhs8a, 60
|
||||
%val8a = sub i64 0, %shift8a
|
||||
store volatile i64 %val8a, i64* @var64
|
||||
; CHECK: neg {{x[0-9]+}}, {{x[0-9]+}}, lsl #60
|
||||
; GISEL: negs {{x[0-9]+}}, {{x[0-9]+}}, lsl #60
|
||||
|
||||
ret void
|
||||
; CHECK: ret
|
||||
|
|
@ -93,67 +82,56 @@ define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
|
|||
%val1 = add i32 %lhs32, %shift1
|
||||
store volatile i32 %val1, i32* @var32
|
||||
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #18
|
||||
; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #18
|
||||
|
||||
%shift2 = lshr i32 %rhs32, 31
|
||||
%val2 = add i32 %shift2, %lhs32
|
||||
store volatile i32 %val2, i32* @var32
|
||||
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #31
|
||||
; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #31
|
||||
|
||||
%shift3 = lshr i32 %rhs32, 5
|
||||
%val3 = sub i32 %lhs32, %shift3
|
||||
store volatile i32 %val3, i32* @var32
|
||||
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #5
|
||||
; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #5
|
||||
|
||||
; Subtraction is not commutative!
|
||||
%shift4 = lshr i32 %rhs32, 19
|
||||
%val4 = sub i32 %shift4, %lhs32
|
||||
store volatile i32 %val4, i32* @var32
|
||||
; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #19
|
||||
; GISEL-NOT: sub{{[s]?}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #19
|
||||
|
||||
%shift4a = lshr i32 %lhs32, 15
|
||||
%val4a = sub i32 0, %shift4a
|
||||
store volatile i32 %val4a, i32* @var32
|
||||
; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, lsr #15
|
||||
; GISEL: negs {{w[0-9]+}}, {{w[0-9]+}}, lsr #15
|
||||
|
||||
%shift5 = lshr i64 %rhs64, 18
|
||||
%val5 = add i64 %lhs64, %shift5
|
||||
store volatile i64 %val5, i64* @var64
|
||||
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #18
|
||||
; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #18
|
||||
|
||||
%shift6 = lshr i64 %rhs64, 31
|
||||
%val6 = add i64 %shift6, %lhs64
|
||||
store volatile i64 %val6, i64* @var64
|
||||
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #31
|
||||
; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #31
|
||||
|
||||
%shift7 = lshr i64 %rhs64, 5
|
||||
%val7 = sub i64 %lhs64, %shift7
|
||||
store volatile i64 %val7, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #5
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #5
|
||||
|
||||
; Subtraction is not commutative!
|
||||
%shift8 = lshr i64 %rhs64, 19
|
||||
%val8 = sub i64 %shift8, %lhs64
|
||||
store volatile i64 %val8, i64* @var64
|
||||
; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #19
|
||||
; GISEL-NOT: sub{{[s]?}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #19
|
||||
|
||||
%shift8a = lshr i64 %lhs64, 45
|
||||
%val8a = sub i64 0, %shift8a
|
||||
store volatile i64 %val8a, i64* @var64
|
||||
; CHECK: neg {{x[0-9]+}}, {{x[0-9]+}}, lsr #45
|
||||
; GISEL: negs {{x[0-9]+}}, {{x[0-9]+}}, lsr #45
|
||||
|
||||
ret void
|
||||
; CHECK: ret
|
||||
; GISEL: ret
|
||||
}
|
||||
|
||||
define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
|
||||
|
|
@ -163,63 +141,53 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
|
|||
%val1 = add i32 %lhs32, %shift1
|
||||
store volatile i32 %val1, i32* @var32
|
||||
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #18
|
||||
; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #18
|
||||
|
||||
%shift2 = ashr i32 %rhs32, 31
|
||||
%val2 = add i32 %shift2, %lhs32
|
||||
store volatile i32 %val2, i32* @var32
|
||||
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #31
|
||||
; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #31
|
||||
|
||||
%shift3 = ashr i32 %rhs32, 5
|
||||
%val3 = sub i32 %lhs32, %shift3
|
||||
store volatile i32 %val3, i32* @var32
|
||||
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #5
|
||||
; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #5
|
||||
|
||||
; Subtraction is not commutative!
|
||||
%shift4 = ashr i32 %rhs32, 19
|
||||
%val4 = sub i32 %shift4, %lhs32
|
||||
store volatile i32 %val4, i32* @var32
|
||||
; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #19
|
||||
; GISEL-NOT: sub{{[s]?}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #19
|
||||
|
||||
%shift4a = ashr i32 %lhs32, 15
|
||||
%val4a = sub i32 0, %shift4a
|
||||
store volatile i32 %val4a, i32* @var32
|
||||
; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, asr #15
|
||||
; GISEL: negs {{w[0-9]+}}, {{w[0-9]+}}, asr #15
|
||||
|
||||
%shift5 = ashr i64 %rhs64, 18
|
||||
%val5 = add i64 %lhs64, %shift5
|
||||
store volatile i64 %val5, i64* @var64
|
||||
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #18
|
||||
; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #18
|
||||
|
||||
%shift6 = ashr i64 %rhs64, 31
|
||||
%val6 = add i64 %shift6, %lhs64
|
||||
store volatile i64 %val6, i64* @var64
|
||||
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #31
|
||||
; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #31
|
||||
|
||||
%shift7 = ashr i64 %rhs64, 5
|
||||
%val7 = sub i64 %lhs64, %shift7
|
||||
store volatile i64 %val7, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #5
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #5
|
||||
|
||||
; Subtraction is not commutative!
|
||||
%shift8 = ashr i64 %rhs64, 19
|
||||
%val8 = sub i64 %shift8, %lhs64
|
||||
store volatile i64 %val8, i64* @var64
|
||||
; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #19
|
||||
; GISEL-NOT: sub{{[s]?}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #19
|
||||
|
||||
%shift8a = ashr i64 %lhs64, 45
|
||||
%val8a = sub i64 0, %shift8a
|
||||
store volatile i64 %val8a, i64* @var64
|
||||
; CHECK: neg {{x[0-9]+}}, {{x[0-9]+}}, asr #45
|
||||
; GISEL: negs {{x[0-9]+}}, {{x[0-9]+}}, asr #45
|
||||
|
||||
ret void
|
||||
; CHECK: ret
|
||||
|
|
@ -288,8 +256,6 @@ define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
|
|||
; 0 then the results will differ.
|
||||
; CHECK: neg [[RHS:w[0-9]+]], {{w[0-9]+}}, lsl #13
|
||||
; CHECK: cmp {{w[0-9]+}}, [[RHS]]
|
||||
; GISEL: negs [[RHS:w[0-9]+]], {{w[0-9]+}}, lsl #13
|
||||
; GISEL: cmp {{w[0-9]+}}, [[RHS]]
|
||||
|
||||
t2:
|
||||
%shift2 = lshr i32 %rhs32, 20
|
||||
|
|
@ -313,8 +279,6 @@ t4:
|
|||
; Again, it's important that cmn isn't used here in case %rhs64 == 0.
|
||||
; CHECK: neg [[RHS:x[0-9]+]], {{x[0-9]+}}, lsl #43
|
||||
; CHECK: cmp {{x[0-9]+}}, [[RHS]]
|
||||
; GISEL: negs [[RHS:x[0-9]+]], {{x[0-9]+}}, lsl #43
|
||||
; GISEL: cmp {{x[0-9]+}}, [[RHS]]
|
||||
|
||||
t5:
|
||||
%shift5 = lshr i64 %rhs64, 20
|
||||
|
|
@ -336,5 +300,4 @@ end:
|
|||
|
||||
ret i32 0
|
||||
; CHECK: ret
|
||||
; GISEL: ret
|
||||
}
|
||||
|
|
|
|||
|
|
@ -104,26 +104,26 @@ define void @sub_i8rhs() minsize {
|
|||
%res32_zext = sub i32 %lhs32, %rhs32_zext
|
||||
store volatile i32 %res32_zext, i32* @var32
|
||||
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
|
||||
; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
|
||||
; GISEL: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
|
||||
|
||||
%rhs32_zext_shift = shl i32 %rhs32_zext, 3
|
||||
%res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
|
||||
store volatile i32 %res32_zext_shift, i32* @var32
|
||||
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
|
||||
; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
|
||||
; GISEL: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
|
||||
|
||||
; Zero-extending to 64-bits
|
||||
%rhs64_zext = zext i8 %val8 to i64
|
||||
%res64_zext = sub i64 %lhs64, %rhs64_zext
|
||||
store volatile i64 %res64_zext, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
|
||||
; GISEL: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
|
||||
|
||||
%rhs64_zext_shift = shl i64 %rhs64_zext, 1
|
||||
%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
|
||||
store volatile i64 %res64_zext_shift, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
|
||||
; GISEL: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
|
||||
|
||||
; Sign-extending to 32-bits
|
||||
%rhs32_sext = sext i8 %val8 to i32
|
||||
|
|
@ -245,26 +245,26 @@ define void @sub_i16rhs() minsize {
|
|||
%res32_zext = sub i32 %lhs32, %rhs32_zext
|
||||
store volatile i32 %res32_zext, i32* @var32
|
||||
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
|
||||
; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
|
||||
; GISEL: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
|
||||
|
||||
%rhs32_zext_shift = shl i32 %rhs32_zext, 3
|
||||
%res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
|
||||
store volatile i32 %res32_zext_shift, i32* @var32
|
||||
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
|
||||
; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
|
||||
; GISEL: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
|
||||
|
||||
; Zero-extending to 64-bits
|
||||
%rhs64_zext = zext i16 %val16 to i64
|
||||
%res64_zext = sub i64 %lhs64, %rhs64_zext
|
||||
store volatile i64 %res64_zext, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
|
||||
; GISEL: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
|
||||
|
||||
%rhs64_zext_shift = shl i64 %rhs64_zext, 1
|
||||
%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
|
||||
store volatile i64 %res64_zext_shift, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
|
||||
; GISEL: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
|
||||
|
||||
; Sign-extending to 32-bits
|
||||
%rhs32_sext = sext i16 %val16 to i32
|
||||
|
|
@ -341,14 +341,14 @@ define void @sub_i32rhs(i32 %in32) minsize {
|
|||
%res64_zext = sub i64 %lhs64, %rhs64_zext
|
||||
store volatile i64 %res64_zext, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
|
||||
; GISEL: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
|
||||
|
||||
%rhs64_zext2 = zext i32 %val32 to i64
|
||||
%rhs64_zext_shift = shl i64 %rhs64_zext2, 2
|
||||
%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
|
||||
store volatile i64 %res64_zext_shift, i64* @var64
|
||||
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
|
||||
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
|
||||
; GISEL: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
|
||||
|
||||
%rhs64_sext = sext i32 %val32 to i64
|
||||
%res64_sext = sub i64 %lhs64, %rhs64_sext
|
||||
|
|
@ -390,7 +390,7 @@ entry:
|
|||
%m = and i32 %x, 3
|
||||
%ext = zext i32 %m to i64
|
||||
; CHECK-NEXT: neg x0, x[[TMP]]
|
||||
; GISEL: negs x0, x[[TMP]]
|
||||
; GISEL: neg x0, x[[TMP]]
|
||||
%ret = sub i64 0, %ext
|
||||
ret i64 %ret
|
||||
}
|
||||
|
|
@ -452,7 +452,7 @@ entry:
|
|||
%m = and i32 %x, 3
|
||||
%ext = zext i32 %m to i64
|
||||
; CHECK-NEXT: sub x0, x[[TMP]], #1
|
||||
; GISEL: subs x0, x[[TMP]], #1
|
||||
; GISEL: sub x0, x[[TMP]], #1
|
||||
%ret = add i64 %ext, -1
|
||||
ret i64 %ret
|
||||
}
|
||||
|
|
|
|||
|
|
@ -141,6 +141,7 @@ static_library("LLVMAArch64CodeGen") {
|
|||
"GISel/AArch64PostLegalizerCombiner.cpp",
|
||||
"GISel/AArch64PostLegalizerLowering.cpp",
|
||||
"GISel/AArch64PreLegalizerCombiner.cpp",
|
||||
"GISel/AArch64PostSelectOptimize.cpp"
|
||||
"GISel/AArch64RegisterBankInfo.cpp",
|
||||
"SVEIntrinsicOpts.cpp",
|
||||
]
|
||||
|
|
|
|||
Loading…
Reference in New Issue