[AArch64] Regenerate merge-store tests. NFCI.

Prep work for an upcoming patch

llvm-svn: 364203
This commit is contained in:
Simon Pilgrim 2019-06-24 16:57:12 +00:00
parent f336eb344c
commit 0f0bbbd4bb
1 changed files with 31 additions and 13 deletions

View File

@ -1,13 +1,28 @@
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s --check-prefix=SPLITTING --check-prefix=CHECK ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK ; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s --check-prefixes=CHECK,SPLITTING
; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefixes=CHECK,MISALIGNED
@g0 = external global <3 x float>, align 16 @g0 = external global <3 x float>, align 16
@g1 = external global <3 x float>, align 4 @g1 = external global <3 x float>, align 4
; CHECK: ldr q[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]], :lo12:g0
; CHECK: str d[[R0]]
define void @blam() { define void @blam() {
; SPLITTING-LABEL: blam:
; SPLITTING: // %bb.0:
; SPLITTING-NEXT: adrp x8, g1
; SPLITTING-NEXT: add x8, x8, :lo12:g1
; SPLITTING-NEXT: adrp x9, g0
; SPLITTING-NEXT: ldr q0, [x9, :lo12:g0]
; SPLITTING-NEXT: str d0, [x8]
; SPLITTING-NEXT: ret
;
; MISALIGNED-LABEL: blam:
; MISALIGNED: // %bb.0:
; MISALIGNED-NEXT: adrp x8, g0
; MISALIGNED-NEXT: ldr q0, [x8, :lo12:g0]
; MISALIGNED-NEXT: adrp x8, g1
; MISALIGNED-NEXT: add x8, x8, :lo12:g1
; MISALIGNED-NEXT: str d0, [x8]
; MISALIGNED-NEXT: ret
%tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0 %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0
%tmp5 = load <3 x float>, <3 x float>* @g0, align 16 %tmp5 = load <3 x float>, <3 x float>* @g0, align 16
%tmp6 = extractelement <3 x float> %tmp5, i64 0 %tmp6 = extractelement <3 x float> %tmp5, i64 0
@ -27,6 +42,17 @@ define void @blam() {
; the fastness of unaligned accesses was not specified correctly. ; the fastness of unaligned accesses was not specified correctly.
define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) { define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
; SPLITTING-LABEL: merge_vec_extract_stores:
; SPLITTING: // %bb.0:
; SPLITTING-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; SPLITTING-NEXT: str d0, [x0, #24]
; SPLITTING-NEXT: str d1, [x0, #32]
; SPLITTING-NEXT: ret
;
; MISALIGNED-LABEL: merge_vec_extract_stores:
; MISALIGNED: // %bb.0:
; MISALIGNED-NEXT: stur q0, [x0, #24]
; MISALIGNED-NEXT: ret
%idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3 %idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3
%idx1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 4 %idx1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 4
@ -37,16 +63,8 @@ define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
store <2 x float> %shuffle1, <2 x float>* %idx1, align 8 store <2 x float> %shuffle1, <2 x float>* %idx1, align 8
ret void ret void
; MISALIGNED-LABEL: merge_vec_extract_stores
; MISALIGNED: stur q0, [x0, #24]
; MISALIGNED-NEXT: ret
; FIXME: Ideally we would like to use a generic target for this test, but this relies ; FIXME: Ideally we would like to use a generic target for this test, but this relies
; on suppressing store pairs. ; on suppressing store pairs.
; SPLITTING-LABEL: merge_vec_extract_stores
; SPLITTING: ext v1.16b, v0.16b, v0.16b, #8
; SPLITTING-NEXT: str d0, [x0, #24]
; SPLITTING-NEXT: str d1, [x0, #32]
; SPLITTING-NEXT: ret
} }