forked from OSchip/llvm-project
Some SSE1 intrinsics: min, max, sqrt, etc.
llvm-svn: 27384
This commit is contained in:
Evan Cheng
parent
bf0016f2d4
commit
0ef83c83e1
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@ -171,6 +171,45 @@ class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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//===----------------------------------------------------------------------===//
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// Helpers for defining instructions that directly correspond to intrinsics.
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class SS_Intrr<bits<8> o, string asm, Intrinsic IntId, ValueType Ty>
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: SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
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[(set VR128:$dst, (Ty (IntId VR128:$src1, VR128:$src2)))]>;
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class SS_Intrm<bits<8> o, string asm, Intrinsic IntId, ValueType Ty>
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: SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
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[(set VR128:$dst, (Ty (IntId VR128:$src1, (load addr:$src2))))]>;
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class SD_Intrr<bits<8> o, string asm, Intrinsic IntId, ValueType Ty>
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: SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
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[(set VR128:$dst, (Ty (IntId VR128:$src1, VR128:$src2)))]>;
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class SD_Intrm<bits<8> o, string asm, Intrinsic IntId, ValueType Ty>
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: SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
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[(set VR128:$dst, (Ty (IntId VR128:$src1, (load addr:$src2))))]>;
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class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
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: PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
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[(set VR128:$dst, (IntId VR128:$src))]>;
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class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
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: PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
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[(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
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class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
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: PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
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[(set VR128:$dst, (IntId VR128:$src))]>;
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class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
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: PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
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[(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
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class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
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: PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
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[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
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class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
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: PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
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[(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
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class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
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: PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
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[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
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class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
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: PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
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[(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
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class S3S_Intrr<bits<8> o, string asm, Intrinsic IntId>
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: S3SI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
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[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
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@ -435,46 +474,22 @@ def Int_RCPSSrm : SSI<0x53, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
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(load addr:$src)))]>;
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let isTwoAddress = 1 in {
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def Int_MAXSSrr : SSI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
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VR128:$src2),
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"maxss {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1,
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VR128:$src2))]>;
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def Int_MAXSSrm : SSI<0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
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f32mem:$src2),
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"maxss {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1,
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(load addr:$src2)))]>;
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def Int_MAXSDrr : SDI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
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VR128:$src2),
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"maxsd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1,
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VR128:$src2))]>;
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def Int_MAXSDrm : SDI<0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
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f64mem:$src2),
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"maxsd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1,
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(load addr:$src2)))]>;
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def Int_MINSSrr : SSI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
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VR128:$src2),
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"minss {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1,
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VR128:$src2))]>;
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def Int_MINSSrm : SSI<0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
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f32mem:$src2),
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"minss {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1,
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(load addr:$src2)))]>;
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def Int_MINSDrr : SDI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
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VR128:$src2),
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"minsd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_min_sd VR128:$src1,
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VR128:$src2))]>;
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def Int_MINSDrm : SDI<0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
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f64mem:$src2),
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"minsd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_min_sd VR128:$src1,
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(load addr:$src2)))]>;
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def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
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int_x86_sse_max_ss, v4f32>;
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def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
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int_x86_sse_max_ss, v4f32>;
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def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
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int_x86_sse2_max_sd, v2f64>;
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def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
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int_x86_sse2_max_sd, v2f64>;
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def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
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int_x86_sse_min_ss, v4f32>;
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def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
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int_x86_sse_min_ss, v4f32>;
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def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
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int_x86_sse2_min_sd, v2f64>;
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def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
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int_x86_sse2_min_sd, v2f64>;
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}
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// Conversion instructions
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@ -863,44 +878,42 @@ def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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(load addr:$src2))))]>;
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}
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def SQRTPSrr : PSI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"sqrtps {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (fsqrt VR128:$src)))]>;
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def SQRTPSrm : PSI<0x51, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"sqrtps {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (fsqrt (load addr:$src))))]>;
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def SQRTPDrr : PDI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"sqrtpd {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v2f64 (fsqrt VR128:$src)))]>;
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def SQRTPDrm : PDI<0x51, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"sqrtpd {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v2f64 (fsqrt (load addr:$src))))]>;
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def SQRTPSrr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
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int_x86_sse_sqrt_ps>;
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def SQRTPSrm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
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int_x86_sse_sqrt_ps>;
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def SQRTPDrr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
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int_x86_sse2_sqrt_pd>;
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def SQRTPDrm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
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int_x86_sse2_sqrt_pd>;
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def RSQRTPSrr : PSI<0x52, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"rsqrtps {$src, $dst|$dst, $src}", []>;
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def RSQRTPSrm : PSI<0x52, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"rsqrtps {$src, $dst|$dst, $src}", []>;
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def RCPPSrr : PSI<0x53, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"rcpps {$src, $dst|$dst, $src}", []>;
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def RCPPSrm : PSI<0x53, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"rcpps {$src, $dst|$dst, $src}", []>;
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def RSQRTPSrr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
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int_x86_sse_rsqrt_ps>;
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def RSQRTPSrm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
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int_x86_sse_rsqrt_ps>;
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def RCPPSrr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
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int_x86_sse_rcp_ps>;
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def RCPPSrm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
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int_x86_sse_rcp_ps>;
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def MAXPSrr : PSI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"maxps {$src, $dst|$dst, $src}", []>;
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def MAXPSrm : PSI<0x5F, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"maxps {$src, $dst|$dst, $src}", []>;
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def MAXPDrr : PDI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"maxpd {$src, $dst|$dst, $src}", []>;
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def MAXPDrm : PDI<0x5F, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"maxpd {$src, $dst|$dst, $src}", []>;
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def MINPSrr : PSI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"minps {$src, $dst|$dst, $src}", []>;
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def MINPSrm : PSI<0x5D, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"minps {$src, $dst|$dst, $src}", []>;
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def MINPDrr : PDI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"minpd {$src, $dst|$dst, $src}", []>;
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def MINPDrm : PDI<0x5D, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"minpd {$src, $dst|$dst, $src}", []>;
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let isTwoAddress = 1 in {
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def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
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int_x86_sse_max_ps>;
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def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
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int_x86_sse_max_ps>;
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def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
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int_x86_sse2_max_pd>;
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def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
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int_x86_sse2_max_pd>;
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def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
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int_x86_sse_min_ps>;
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def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
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int_x86_sse_min_ps>;
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def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
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int_x86_sse2_min_pd>;
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def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
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int_x86_sse2_min_pd>;
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}
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// Logical
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let isTwoAddress = 1 in {
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