From 0ee8c513f7e6a417b1259e6705b36a0efa91e214 Mon Sep 17 00:00:00 2001
From: Chad Rosier <mcrosier@apple.com>
Date: Wed, 8 Feb 2012 02:45:44 +0000
Subject: [PATCH] [fast-isel] Add support for SUBs with non-legal types.

llvm-svn: 150047
---
 llvm/lib/Target/ARM/ARMFastISel.cpp       |  5 +++
 llvm/test/CodeGen/ARM/fast-isel-binary.ll | 38 +++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index faa3e5920ef3..39b3bd4bdedc 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -1749,6 +1749,9 @@ bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
     case ISD::OR:
       Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
       break;
+    case ISD::SUB:
+      Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
+      break;
   }
 
   unsigned SrcReg1 = getRegForValue(I->getOperand(0));
@@ -2509,6 +2512,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
       return SelectBinaryIntOp(I, ISD::ADD);
     case Instruction::Or:
       return SelectBinaryIntOp(I, ISD::OR);
+    case Instruction::Sub:
+      return SelectBinaryIntOp(I, ISD::SUB);
     case Instruction::FAdd:
       return SelectBinaryFPOp(I, ISD::FADD);
     case Instruction::FSub:
diff --git a/llvm/test/CodeGen/ARM/fast-isel-binary.ll b/llvm/test/CodeGen/ARM/fast-isel-binary.ll
index b15949c4f3bb..723383e04b8e 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-binary.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-binary.ll
@@ -76,3 +76,41 @@ entry:
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
+
+; Test sub with non-legal types
+
+define void @sub_i1(i1 %a, i1 %b) nounwind ssp {
+entry:
+; ARM: sub_i1
+; THUMB: sub_i1
+  %a.addr = alloca i1, align 4
+  %0 = sub i1 %a, %b
+; ARM: sub r0, r0, r1
+; THUMB: subs r0, r0, r1
+  store i1 %0, i1* %a.addr, align 4
+  ret void
+}
+
+define void @sub_i8(i8 %a, i8 %b) nounwind ssp {
+entry:
+; ARM: sub_i8
+; THUMB: sub_i8
+  %a.addr = alloca i8, align 4
+  %0 = sub i8 %a, %b
+; ARM: sub r0, r0, r1
+; THUMB: subs r0, r0, r1
+  store i8 %0, i8* %a.addr, align 4
+  ret void
+}
+
+define void @sub_i16(i16 %a, i16 %b) nounwind ssp {
+entry:
+; ARM: sub_i16
+; THUMB: sub_i16
+  %a.addr = alloca i16, align 4
+  %0 = sub i16 %a, %b
+; ARM: sub r0, r0, r1
+; THUMB: subs r0, r0, r1
+  store i16 %0, i16* %a.addr, align 4
+  ret void
+}