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[IPRA] Don't rely on non-exact function definitions 

If a function definition is not exact, then the linker could select a
differently-compiled version of it, which could use different registers.

https://reviews.llvm.org/D64909

llvm-svn: 366557
This commit is contained in:
Oliver Stannard 2019-07-19 09:59:26 +00:00
parent 0b001f94a5
commit 0ed7732671
2 changed files with 49 additions and 1 deletions
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6
llvm/lib/CodeGen/RegUsageInfoPropagate.cpp
View File

@ -130,7 +130,11 @@ bool RegUsageInfoPropagation::runOnMachineFunction(MachineFunction &MF) {
};
if (const Function *F = findCalledFunction(M, MI)) {
UpdateRegMask(*F);
if (F->isDefinitionExact()) {
UpdateRegMask(*F);
} else {
LLVM_DEBUG(dbgs() << "Function definition is not exact\n");
}
} else {
LLVM_DEBUG(dbgs() << "Failed to find call target function\n");
}

44
llvm/test/CodeGen/ARM/ipra-exact-definition.ll Normal file
View File

@ -0,0 +1,44 @@
; RUN: llc -mtriple armv7a--none-eabi < %s -enable-ipra | FileCheck %s
; A linkone_odr function (the same applies to available_externally, linkonce,
; weak, common, extern_weak and weak_odr) could be replaced with a
; differently-compiled version of the same source at link time, which might use
; different registers, so we can't do IPRA on it.
define linkonce_odr void @leaf_linkonce_odr() {
entry:
ret void
}
define void @test_linkonce_odr() {
; CHECK-LABEL: test_linkonce_odr:
entry:
; CHECK: ASM1: r3
; CHECK: mov [[TEMP:r[0-9]+]], r3
; CHECK: bl leaf_linkonce_odr
; CHECK: mov r3, [[TEMP]]
; CHECK: ASM2: r3
%0 = tail call i32 asm sideeffect "// ASM1: $0", "={r3},0"(i32 undef)
tail call void @leaf_linkonce_odr()
%1 = tail call i32 asm sideeffect "// ASM2: $0", "={r3},0"(i32 %0)
ret void
}
; This function has external linkage (the same applies to private, internal and
; appending), so the version we see here is guaranteed to be the version
; selected by the linker, so we can do IPRA.
define external void @leaf_external() {
entry:
ret void
}
define void @test_external() {
; CHECK-LABEL: test_external:
entry:
; CHECK: ASM1: r3
; CHECK-NOT: r3
; CHECK: bl leaf_external
; CHECK-NOT: r3
; CHECK: ASM2: r3
%0 = tail call i32 asm sideeffect "// ASM1: $0", "={r3},0"(i32 undef)
tail call void @leaf_external()
%1 = tail call i32 asm sideeffect "// ASM2: $0", "={r3},0"(i32 %0)
ret void
}