forked from OSchip/llvm-project
[RISCV] Reduce duplicate FP test cases.
-Remove feq, fle, flt tests from *-arith.ll in favor of *-fcmp.ll which tests all predicates. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D113703
This commit is contained in:
Craig Topper
parent
64e171c2d0
commit
0ec5f1e64f
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@ -8,9 +8,10 @@
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; These tests are each targeted at a particular RISC-V FPU instruction. Most
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; other files in this folder exercise LLVM IR instructions that don't directly
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; match a RISC-V instruction.
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; These tests are each targeted at a particular RISC-V FPU instruction.
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; Compares and conversions can be found in double-fcmp.ll and double-convert.ll
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; respectively. Some other double-*.ll files in this folder exercise LLVM IR
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; instructions that don't directly match a RISC-V instruction.
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define double @fadd_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fadd_d:
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@ -568,141 +569,6 @@ define double @fmax_d(double %a, double %b) nounwind {
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ret double %1
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}
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define i32 @feq_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: feq_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: feq.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: feq_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: feq.d a0, ft1, ft0
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; RV64IFD-NEXT: ret
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;
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; RV32I-LABEL: feq_d:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __eqdf2@plt
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: feq_d:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __eqdf2@plt
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = fcmp oeq double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @flt_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: flt_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: flt_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: flt.d a0, ft1, ft0
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; RV64IFD-NEXT: ret
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;
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; RV32I-LABEL: flt_d:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __ltdf2@plt
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; RV32I-NEXT: slti a0, a0, 0
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: flt_d:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __ltdf2@plt
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; RV64I-NEXT: slti a0, a0, 0
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = fcmp olt double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fle_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fle_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fle.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fle_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fle.d a0, ft1, ft0
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; RV64IFD-NEXT: ret
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;
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; RV32I-LABEL: fle_d:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __ledf2@plt
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; RV32I-NEXT: slti a0, a0, 1
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fle_d:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __ledf2@plt
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; RV64I-NEXT: slti a0, a0, 1
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = fcmp ole double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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declare double @llvm.fma.f64(double, double, double)
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define double @fmadd_d(double %a, double %b, double %c) nounwind {
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@ -8,9 +8,10 @@
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; These tests are each targeted at a particular RISC-V FPU instruction. Most
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; other files in this folder exercise LLVM IR instructions that don't directly
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; match a RISC-V instruction.
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; These tests are each targeted at a particular RISC-V FPU instruction.
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; Compares and conversions can be found in float-fcmp.ll and float-convert.ll
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; respectively. Some other float-*.ll files in this folder exercise LLVM IR
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; instructions that don't directly match a RISC-V instruction.
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define float @fadd_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fadd_s:
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@ -495,123 +496,6 @@ define float @fmax_s(float %a, float %b) nounwind {
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ret float %1
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}
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define i32 @feq_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: feq_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: feq.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: feq_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: feq.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: feq_s:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __eqsf2@plt
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: feq_s:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __eqsf2@plt
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = fcmp oeq float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @flt_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: flt_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: flt.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: flt_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: flt.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: flt_s:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __ltsf2@plt
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; RV32I-NEXT: slti a0, a0, 0
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: flt_s:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __ltsf2@plt
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; RV64I-NEXT: slti a0, a0, 0
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = fcmp olt float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fle_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fle_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fle.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fle_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fle.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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;
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; RV32I-LABEL: fle_s:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __lesf2@plt
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; RV32I-NEXT: slti a0, a0, 1
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fle_s:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __lesf2@plt
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; RV64I-NEXT: slti a0, a0, 1
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = fcmp ole float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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declare float @llvm.fma.f32(float, float, float)
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define float @fmadd_s(float %a, float %b, float %c) nounwind {
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@ -8,9 +8,10 @@
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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|
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; These tests are each targeted at a particular RISC-V FPU instruction. Most
|
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; other files in this folder exercise LLVM IR instructions that don't directly
|
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; match a RISC-V instruction.
|
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; These tests are each targeted at a particular RISC-V FPU instruction.
|
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; Compares and conversions can be found in half-fcmp.ll and half-convert.ll
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; respectively. Some other half-*.ll files in this folder exercise LLVM IR
|
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; instructions that don't directly match a RISC-V instruction.
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define half @fadd_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fadd_s:
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@ -777,207 +778,6 @@ define half @fmax_s(half %a, half %b) nounwind {
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ret half %1
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}
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define i32 @feq_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: feq_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: feq_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa1
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; RV64IZFH-NEXT: ret
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;
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; RV32I-LABEL: feq_s:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv s2, a1
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; RV32I-NEXT: lui a1, 16
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; RV32I-NEXT: addi s0, a1, -1
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; RV32I-NEXT: and a0, a0, s0
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; RV32I-NEXT: call __gnu_h2f_ieee@plt
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; RV32I-NEXT: mv s1, a0
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; RV32I-NEXT: and a0, s2, s0
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; RV32I-NEXT: call __gnu_h2f_ieee@plt
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: mv a0, s1
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; RV32I-NEXT: call __eqsf2@plt
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: feq_s:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -32
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; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
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; RV64I-NEXT: mv s2, a1
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; RV64I-NEXT: lui a1, 16
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; RV64I-NEXT: addiw s0, a1, -1
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; RV64I-NEXT: and a0, a0, s0
|
||||
; RV64I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV64I-NEXT: mv s1, a0
|
||||
; RV64I-NEXT: and a0, s2, s0
|
||||
; RV64I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV64I-NEXT: mv a1, a0
|
||||
; RV64I-NEXT: mv a0, s1
|
||||
; RV64I-NEXT: call __eqsf2@plt
|
||||
; RV64I-NEXT: seqz a0, a0
|
||||
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 32
|
||||
; RV64I-NEXT: ret
|
||||
%1 = fcmp oeq half %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @flt_s(half %a, half %b) nounwind {
|
||||
; RV32IZFH-LABEL: flt_s:
|
||||
; RV32IZFH: # %bb.0:
|
||||
; RV32IZFH-NEXT: flt.h a0, fa0, fa1
|
||||
; RV32IZFH-NEXT: ret
|
||||
;
|
||||
; RV64IZFH-LABEL: flt_s:
|
||||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
|
||||
; RV64IZFH-NEXT: ret
|
||||
;
|
||||
; RV32I-LABEL: flt_s:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: mv s2, a1
|
||||
; RV32I-NEXT: lui a1, 16
|
||||
; RV32I-NEXT: addi s0, a1, -1
|
||||
; RV32I-NEXT: and a0, a0, s0
|
||||
; RV32I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV32I-NEXT: mv s1, a0
|
||||
; RV32I-NEXT: and a0, s2, s0
|
||||
; RV32I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV32I-NEXT: mv a1, a0
|
||||
; RV32I-NEXT: mv a0, s1
|
||||
; RV32I-NEXT: call __ltsf2@plt
|
||||
; RV32I-NEXT: slti a0, a0, 0
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: flt_s:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -32
|
||||
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: mv s2, a1
|
||||
; RV64I-NEXT: lui a1, 16
|
||||
; RV64I-NEXT: addiw s0, a1, -1
|
||||
; RV64I-NEXT: and a0, a0, s0
|
||||
; RV64I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV64I-NEXT: mv s1, a0
|
||||
; RV64I-NEXT: and a0, s2, s0
|
||||
; RV64I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV64I-NEXT: mv a1, a0
|
||||
; RV64I-NEXT: mv a0, s1
|
||||
; RV64I-NEXT: call __ltsf2@plt
|
||||
; RV64I-NEXT: slti a0, a0, 0
|
||||
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 32
|
||||
; RV64I-NEXT: ret
|
||||
%1 = fcmp olt half %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @fle_s(half %a, half %b) nounwind {
|
||||
; RV32IZFH-LABEL: fle_s:
|
||||
; RV32IZFH: # %bb.0:
|
||||
; RV32IZFH-NEXT: fle.h a0, fa0, fa1
|
||||
; RV32IZFH-NEXT: ret
|
||||
;
|
||||
; RV64IZFH-LABEL: fle_s:
|
||||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
|
||||
; RV64IZFH-NEXT: ret
|
||||
;
|
||||
; RV32I-LABEL: fle_s:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: mv s2, a1
|
||||
; RV32I-NEXT: lui a1, 16
|
||||
; RV32I-NEXT: addi s0, a1, -1
|
||||
; RV32I-NEXT: and a0, a0, s0
|
||||
; RV32I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV32I-NEXT: mv s1, a0
|
||||
; RV32I-NEXT: and a0, s2, s0
|
||||
; RV32I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV32I-NEXT: mv a1, a0
|
||||
; RV32I-NEXT: mv a0, s1
|
||||
; RV32I-NEXT: call __lesf2@plt
|
||||
; RV32I-NEXT: slti a0, a0, 1
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: fle_s:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -32
|
||||
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: mv s2, a1
|
||||
; RV64I-NEXT: lui a1, 16
|
||||
; RV64I-NEXT: addiw s0, a1, -1
|
||||
; RV64I-NEXT: and a0, a0, s0
|
||||
; RV64I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV64I-NEXT: mv s1, a0
|
||||
; RV64I-NEXT: and a0, s2, s0
|
||||
; RV64I-NEXT: call __gnu_h2f_ieee@plt
|
||||
; RV64I-NEXT: mv a1, a0
|
||||
; RV64I-NEXT: mv a0, s1
|
||||
; RV64I-NEXT: call __lesf2@plt
|
||||
; RV64I-NEXT: slti a0, a0, 1
|
||||
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 32
|
||||
; RV64I-NEXT: ret
|
||||
%1 = fcmp ole half %a, %b
|
||||
%2 = zext i1 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
declare half @llvm.fma.f16(half, half, half)
|
||||
|
||||
define half @fmadd_s(half %a, half %b, half %c) nounwind {
|
||||
|
|
|
|||
Loading…
Reference in New Issue