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Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 

Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
This commit is contained in:
Johnny Chen 2011-04-06 01:18:32 +00:00
parent ae6a89a890
commit 0ec0e98a6a
2 changed files with 7 additions and 8 deletions
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10
llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -547,7 +547,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
return false; return false;
case ARM::SMLAL: case ARM::SMULL: case ARM::UMAAL: case ARM::UMLAL: case ARM::SMLAL: case ARM::SMULL: case ARM::UMAAL: case ARM::UMLAL:
case ARM::UMULL: case ARM::SMLALBB: case ARM::SMLALBT: case ARM::SMLALTB: case ARM::UMULL: case ARM::SMLALBB: case ARM::SMLALBT: case ARM::SMLALTB:
case ARM::SMLALTT: case ARM::SMLSLD: case ARM::SMLALTT: case ARM::SMLSLD: case ARM::SMLSLDX:
if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
return true; return true;
if (R19_16 == R15_12) if (R19_16 == R15_12)
@ -1201,12 +1201,8 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
} }
OpIdx += 1; OpIdx += 1;
} else { } else {
// The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of // If Inst{25} = 1 and Inst{4} != 0, we should reject this as invalid.
// A8.6.86 LDRT. So if Inst{4} != 0 while Inst{25} (getIBit(insn)) == 1, if (slice(insn,4,4) == 1)
// we should reject this insn as invalid.
//
// Ditto for LDRBT.
if ((Opcode == ARM::LDRT || Opcode == ARM::LDRBT) && (slice(insn,4,4) == 1))
return false; return false;
// Disassemble the offset reg (Rm), shift type, and immediate shift length. // Disassemble the offset reg (Rm), shift type, and immediate shift length.

5
llvm/test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -198,7 +198,7 @@
0xa5 0xba 0xd2 0xed 0xa5 0xba 0xd2 0xed
# CHECK: strtvc r5, [r3], r0, lsr #20 # CHECK: strtvc r5, [r3], r0, lsr #20
0x30 0x5a 0xa3 0x76 0x20 0x5a 0xa3 0x76
# CHECK: stmiblo sp, {r0, r4, r8, r11, r12, pc} # CHECK: stmiblo sp, {r0, r4, r8, r11, r12, pc}
0x11 0x99 0x8d 0x39 0x11 0x99 0x8d 0x39
@ -242,3 +242,6 @@
# CHECK: mrchs p2, #3, r11, c13, c6, #6 # CHECK: mrchs p2, #3, r11, c13, c6, #6
0xd6 0xb2 0x7d 0x2e 0xd6 0xb2 0x7d 0x2e
# CHECK: smlsldx r4, r12, r11, r4
0x7b 0x44 0x4c 0xe7