forked from OSchip/llvm-project
Teach ScalarEvolution how to recognize zext-inreg and sext-inreg,
as they appear in LLVM IR. This isn't particularly interesting on its own; this is just setting up some infrastructure. llvm-svn: 69655
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@ -1947,6 +1947,19 @@ SCEVHandle ScalarEvolutionsImpl::createSCEV(Value *V) {
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case Instruction::Sub:
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return SE.getMinusSCEV(getSCEV(U->getOperand(0)),
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getSCEV(U->getOperand(1)));
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case Instruction::And:
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// For an expression like x&255 that merely masks off the high bits,
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// use zext(trunc(x)) as the SCEV expression.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
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const APInt &A = CI->getValue();
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unsigned Ones = A.countTrailingOnes();
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if (APIntOps::isMask(Ones, A))
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return
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SE.getZeroExtendExpr(SE.getTruncateExpr(getSCEV(U->getOperand(0)),
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IntegerType::get(Ones)),
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U->getType());
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}
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break;
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case Instruction::Or:
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// If the RHS of the Or is a constant, we may have something like:
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// X*4+1 which got turned into X*4|1. Handle this as an Add so loop
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@ -1996,6 +2009,20 @@ SCEVHandle ScalarEvolutionsImpl::createSCEV(Value *V) {
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}
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break;
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case Instruction::AShr:
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// For a two-shift sext-inreg, use sext(trunc(x)) as the SCEV expression.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1)))
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if (Instruction *L = dyn_cast<Instruction>(U->getOperand(0)))
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if (L->getOpcode() == Instruction::Shl &&
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L->getOperand(1) == U->getOperand(1)) {
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uint64_t Amt = CI->getZExtValue();
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return
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SE.getSignExtendExpr(SE.getTruncateExpr(getSCEV(L->getOperand(0)),
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IntegerType::get(Amt)),
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U->getType());
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}
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break;
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case Instruction::Trunc:
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return SE.getTruncateExpr(getSCEV(U->getOperand(0)), U->getType());
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