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Add ADD and SUB to the predicable ARM instructions. 

It is not my plan to duplicate the entire ARM instruction set with
predicated versions. We need a way of representing predicated
instructions in SSA form without requiring a separate opcode.

Then the pseudo-instructions can go away.

llvm-svn: 162061
This commit is contained in:
Jakob Stoklund Olesen 2012-08-16 23:21:55 +00:00
parent c19bf0282d
commit 0ea1fce6b4
6 changed files with 86 additions and 21 deletions
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20
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1613,6 +1613,26 @@ static unsigned canFoldIntoMOVCC(unsigned Reg, MachineInstr *&MI,
case ARM::t2ORRri: return ARM::t2ORRCCri;
case ARM::t2ORRrr: return ARM::t2ORRCCrr;
case ARM::t2ORRrs: return ARM::t2ORRCCrs;
// ARM ADD/SUB
case ARM::ADDri: return ARM::ADDCCri;
case ARM::ADDrr: return ARM::ADDCCrr;
case ARM::ADDrsi: return ARM::ADDCCrsi;
case ARM::ADDrsr: return ARM::ADDCCrsr;
case ARM::SUBri: return ARM::SUBCCri;
case ARM::SUBrr: return ARM::SUBCCrr;
case ARM::SUBrsi: return ARM::SUBCCrsi;
case ARM::SUBrsr: return ARM::SUBCCrsr;
// Thumb2 ADD/SUB
case ARM::t2ADDri: return ARM::t2ADDCCri;
case ARM::t2ADDri12: return ARM::t2ADDCCri12;
case ARM::t2ADDrr: return ARM::t2ADDCCrr;
case ARM::t2ADDrs: return ARM::t2ADDCCrs;
case ARM::t2SUBri: return ARM::t2SUBCCri;
case ARM::t2SUBri12: return ARM::t2SUBCCri12;
case ARM::t2SUBrr: return ARM::t2SUBCCrr;
case ARM::t2SUBrs: return ARM::t2SUBCCrs;
}
}

4
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -4023,6 +4023,10 @@ defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
defm ADDCC : AsI1_bincc_irs<ADDri, ADDrr, ADDrsi, ADDrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
defm SUBCC : AsI1_bincc_irs<SUBri, SUBrr, SUBrsi, SUBrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
} // neverHasSideEffects

27
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -757,6 +757,33 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
let Inst{24} = 1;
let Inst{23-21} = op23_21;
}
// Predicated versions.
def CCri : t2PseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPRnopc:$Rn, t2_so_imm:$imm,
pred:$p, cc_out:$s), 4, IIC_iALUi, [],
(!cast<Instruction>(NAME#ri) GPRnopc:$Rd,
GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
def CCri12 : t2PseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPR:$Rn, imm0_4095:$imm,
pred:$p),
4, IIC_iALUi, [],
(!cast<Instruction>(NAME#ri12) GPRnopc:$Rd,
GPR:$Rn, imm0_4095:$imm, pred:$p)>,
RegConstraint<"$Rfalse = $Rd">;
def CCrr : t2PseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPRnopc:$Rn, rGPR:$Rm,
pred:$p, cc_out:$s), 4, IIC_iALUr, [],
(!cast<Instruction>(NAME#rr) GPRnopc:$Rd,
GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
def CCrs : t2PseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPRnopc:$Rn, t2_so_reg:$Rm,
pred:$p, cc_out:$s), 4, IIC_iALUsi, [],
(!cast<Instruction>(NAME#rs) GPRnopc:$Rd,
GPRnopc:$Rn, t2_so_reg:$Rm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
}
/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns

7
llvm/test/CodeGen/ARM/select.ll
View File

@ -76,12 +76,11 @@ define double @f7(double %a, double %b) {
; block generated, odds are good that we have close to the ideal code for this:
;
; CHECK-NEON: _f8:
; CHECK-NEON: movw [[R3:r[0-9]+]], #1123
; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
; CHECK-NEON-NEXT: movw [[R3:r[0-9]+]], #1123
; CHECK-NEON-NEXT: adds {{r.*}}, [[R2]], #4
; CHECK-NEON-NEXT: cmp r0, [[R3]]
; CHECK-NEON-NEXT: it ne
; CHECK-NEON-NEXT: movne {{r.*}}, [[R2]]
; CHECK-NEON-NEXT: it eq
; CHECK-NEON-NEXT: addeq.w {{r.*}}, [[R2]]
; CHECK-NEON-NEXT: ldr
; CHECK-NEON: bx

31
llvm/test/CodeGen/ARM/select_xform.ll
View File

@ -4,13 +4,13 @@
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
; ARM: t1:
; ARM: sub r0, r1, #-2147483647
; ARM: movgt r0, r1
; ARM: suble r1, r1, #-2147483647
; ARM: mov r0, r1
; T2: t1:
; T2: mvn r0, #-2147483648
; T2: add r0, r1
; T2: movgt r0, r1
; T2: addle.w r1, r1
; T2: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
%tmp3 = add i32 %tmp2, %b
@ -19,12 +19,12 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; ARM: t2:
; ARM: sub r0, r1, #10
; ARM: movgt r0, r1
; ARM: suble r1, r1, #10
; ARM: mov r0, r1
; T2: t2:
; T2: sub.w r0, r1, #10
; T2: movgt r0, r1
; T2: suble.w r1, r1, #10
; T2: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 10
%tmp3 = sub i32 %b, %tmp2
@ -164,3 +164,18 @@ define i32 @t11(i32 %a, i32 %b) nounwind {
%tmp1 = select i1 %cond, i32 %x, i32 %a
ret i32 %tmp1
}
; Fold ADDri12 into movcc
define i32 @t12(i32 %a, i32 %b) nounwind {
; ARM: t12:
; ARM: cmp r0, r1
; ARM: addge r0, r1,
; T2: t12:
; T2: cmp r0, r1
; T2: addwge r0, r1, #3000
%x = add i32 %b, 3000
%cond = icmp slt i32 %a, %b
%tmp1 = select i1 %cond, i32 %a, i32 %x
ret i32 %tmp1
}

18
llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll
View File

@ -4,9 +4,9 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
; CHECK: t1
; CHECK: mvn r0, #-2147483648
; CHECK: cmp r2, #10
; CHECK: add r0, r1
; CHECK: it gt
; CHECK: movgt r0, r1
; CHECK: it le
; CHECK: addle.w r1, r1, r0
; CHECK: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
%tmp3 = add i32 %tmp2, %b
@ -15,10 +15,10 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind {
; CHECK: t2
; CHECK: add.w r0, r1, #-2147483648
; CHECK: cmp r2, #10
; CHECK: it gt
; CHECK: movgt r0, r1
; CHECK: it le
; CHECK: addle.w r1, r1, #-2147483648
; CHECK: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 2147483648
@ -28,10 +28,10 @@ define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind {
define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; CHECK: t3
; CHECK: sub.w r0, r1, #10
; CHECK: cmp r2, #10
; CHECK: it gt
; CHECK: movgt r0, r1
; CHECK: it le
; CHECK: suble.w r1, r1, #10
; CHECK: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 10
%tmp3 = sub i32 %b, %tmp2