forked from OSchip/llvm-project
[AMDGPU][MC][GFX11] Add validation of constant bus limitations for VOPD
Differential Revision: https://reviews.llvm.org/D133881
This commit is contained in:
Dmitry Preobrazhensky
parent
c89e60bf1f
commit
0e868aff43
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@ -3468,9 +3468,8 @@ bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
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}
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}
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bool
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AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst,
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const OperandVector &Operands) {
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bool AMDGPUAsmParser::validateConstantBusLimitations(
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const MCInst &Inst, const OperandVector &Operands) {
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const unsigned Opcode = Inst.getOpcode();
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const MCInstrDesc &Desc = MII.get(Opcode);
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unsigned LastSGPR = AMDGPU::NoRegister;
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@ -3478,69 +3477,67 @@ AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst,
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unsigned NumLiterals = 0;
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unsigned LiteralSize;
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if (Desc.TSFlags &
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(SIInstrFlags::VOPC |
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SIInstrFlags::VOP1 | SIInstrFlags::VOP2 |
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SIInstrFlags::VOP3 | SIInstrFlags::VOP3P |
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SIInstrFlags::SDWA)) {
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// Check special imm operands (used by madmk, etc)
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if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) {
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++NumLiterals;
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LiteralSize = 4;
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}
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if (!(Desc.TSFlags &
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(SIInstrFlags::VOPC | SIInstrFlags::VOP1 | SIInstrFlags::VOP2 |
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SIInstrFlags::VOP3 | SIInstrFlags::VOP3P | SIInstrFlags::SDWA)) &&
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!isVOPD(Opcode))
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return true;
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SmallDenseSet<unsigned> SGPRsUsed;
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unsigned SGPRUsed = findImplicitSGPRReadInVOP(Inst);
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if (SGPRUsed != AMDGPU::NoRegister) {
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SGPRsUsed.insert(SGPRUsed);
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++ConstantBusUseCount;
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}
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// Check special imm operands (used by madmk, etc)
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if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) {
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++NumLiterals;
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LiteralSize = 4;
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}
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const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
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const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
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const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
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SmallDenseSet<unsigned> SGPRsUsed;
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unsigned SGPRUsed = findImplicitSGPRReadInVOP(Inst);
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if (SGPRUsed != AMDGPU::NoRegister) {
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SGPRsUsed.insert(SGPRUsed);
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++ConstantBusUseCount;
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}
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const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
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OperandIndices OpIndices = getSrcOperandIndices(Opcode);
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for (int OpIdx : OpIndices) {
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if (OpIdx == -1) break;
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for (int OpIdx : OpIndices) {
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if (OpIdx == -1)
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continue;
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const MCOperand &MO = Inst.getOperand(OpIdx);
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if (usesConstantBus(Inst, OpIdx)) {
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if (MO.isReg()) {
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LastSGPR = mc2PseudoReg(MO.getReg());
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// Pairs of registers with a partial intersections like these
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// s0, s[0:1]
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// flat_scratch_lo, flat_scratch
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// flat_scratch_lo, flat_scratch_hi
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// are theoretically valid but they are disabled anyway.
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// Note that this code mimics SIInstrInfo::verifyInstruction
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if (SGPRsUsed.insert(LastSGPR).second) {
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++ConstantBusUseCount;
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}
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} else { // Expression or a literal
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const MCOperand &MO = Inst.getOperand(OpIdx);
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if (usesConstantBus(Inst, OpIdx)) {
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if (MO.isReg()) {
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LastSGPR = mc2PseudoReg(MO.getReg());
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// Pairs of registers with a partial intersections like these
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// s0, s[0:1]
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// flat_scratch_lo, flat_scratch
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// flat_scratch_lo, flat_scratch_hi
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// are theoretically valid but they are disabled anyway.
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// Note that this code mimics SIInstrInfo::verifyInstruction
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if (SGPRsUsed.insert(LastSGPR).second) {
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++ConstantBusUseCount;
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}
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} else { // Expression or a literal
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if (Desc.OpInfo[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)
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continue; // special operand like VINTERP attr_chan
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if (Desc.OpInfo[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)
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continue; // special operand like VINTERP attr_chan
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// An instruction may use only one literal.
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// This has been validated on the previous step.
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// See validateVOPLiteral.
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// This literal may be used as more than one operand.
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// If all these operands are of the same size,
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// this literal counts as one scalar value.
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// Otherwise it counts as 2 scalar values.
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// See "GFX10 Shader Programming", section 3.6.2.3.
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// An instruction may use only one literal.
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// This has been validated on the previous step.
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// See validateVOPLiteral.
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// This literal may be used as more than one operand.
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// If all these operands are of the same size,
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// this literal counts as one scalar value.
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// Otherwise it counts as 2 scalar values.
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// See "GFX10 Shader Programming", section 3.6.2.3.
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unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx);
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if (Size < 4) Size = 4;
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unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx);
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if (Size < 4)
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Size = 4;
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if (NumLiterals == 0) {
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NumLiterals = 1;
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LiteralSize = Size;
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} else if (LiteralSize != Size) {
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NumLiterals = 2;
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}
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if (NumLiterals == 0) {
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NumLiterals = 1;
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LiteralSize = Size;
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} else if (LiteralSize != Size) {
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NumLiterals = 2;
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}
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}
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}
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@ -72,3 +72,72 @@ v_dual_fmamk_f32 v122, s0, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, s0,
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// GFX11: error: only one literal operand is allowed
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// GFX11-NEXT:{{^}}v_dual_fmamk_f32 v122, s0, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, s0, 0x1234, v162
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// GFX11-NEXT:{{^}} ^
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//===----------------------------------------------------------------------===//
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// A VOPD instruction cannot use more than 2 scalar operands
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//===----------------------------------------------------------------------===//
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// 2 different SGPRs + LITERAL
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v_dual_fmaak_f32 v122, s74, v161, 2.741 :: v_dual_and_b32 v247, s75, v98
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_fmaak_f32 v122, s74, v161, 2.741 :: v_dual_and_b32 v247, s75, v98
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// GFX11-NEXT:{{^}} ^
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v_dual_mov_b32 v247, s73 :: v_dual_fmaak_f32 v122, s74, v161, 2.741
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_mov_b32 v247, s73 :: v_dual_fmaak_f32 v122, s74, v161, 2.741
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// GFX11-NEXT:{{^}} ^
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v_dual_fmamk_f32 v122, s0, 0xbabe, v161 :: v_dual_fmamk_f32 v123, s1, 0xbabe, v162
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_fmamk_f32 v122, s0, 0xbabe, v161 :: v_dual_fmamk_f32 v123, s1, 0xbabe, v162
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// GFX11-NEXT:{{^}} ^
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// 2 different SGPRs + VCC
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v_dual_add_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s2, v3
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_add_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s2, v3
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// GFX11-NEXT:{{^}} ^
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v_dual_cndmask_b32 v6, s1, v3 :: v_dual_add_f32 v255, s2, v2
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_cndmask_b32 v6, s1, v3 :: v_dual_add_f32 v255, s2, v2
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// GFX11-NEXT:{{^}} ^
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v_dual_cndmask_b32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s2, v3
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_cndmask_b32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s2, v3
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// GFX11-NEXT:{{^}} ^
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// SGPR + LITERAL + VCC
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v_dual_cndmask_b32 v255, s1, v2 :: v_dual_mov_b32 v254, 0xbabe
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_cndmask_b32 v255, s1, v2 :: v_dual_mov_b32 v254, 0xbabe
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// GFX11-NEXT:{{^}} ^
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v_dual_cndmask_b32 v255, 0xbabe, v2 :: v_dual_mov_b32 v254, s1
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_cndmask_b32 v255, 0xbabe, v2 :: v_dual_mov_b32 v254, s1
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// GFX11-NEXT:{{^}} ^
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v_dual_cndmask_b32 v255, s3, v2 :: v_dual_fmamk_f32 v254, v1, 0xbabe, v162
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_cndmask_b32 v255, s3, v2 :: v_dual_fmamk_f32 v254, v1, 0xbabe, v162
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// GFX11-NEXT:{{^}} ^
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v_dual_cndmask_b32 v255, v1, v2 :: v_dual_fmamk_f32 v254, s3, 0xbabe, v162
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_cndmask_b32 v255, v1, v2 :: v_dual_fmamk_f32 v254, s3, 0xbabe, v162
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// GFX11-NEXT:{{^}} ^
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// SGPR + VCC + VCC_LO
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// This is a special case because implicit VCC operand has 64 bit size.
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// SP3 does not accept this instruction as well.
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v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, s1, v3
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// GFX11: error: invalid operand (violates constant bus restrictions)
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// GFX11-NEXT:{{^}}v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, s1, v3
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// GFX11-NEXT:{{^}} ^
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@ -39,3 +39,66 @@ v_dual_fmamk_f32 v122, v74, 0xfe0b, v162 :: v_dual_dot2acc_f32_f16 v24
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v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0xdeadbeef, v162
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// GFX11: encoding: [0xff,0x42,0x85,0xc8,0xff,0x44,0x7b,0x7a,0xef,0xbe,0xad,0xde]
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//===----------------------------------------------------------------------===//
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// A VOPD instruction can use 2 scalar operands,
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// but implicit VCC must be counted in.
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//===----------------------------------------------------------------------===//
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// 2 different SGPRs
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v_dual_mul_f32 v0, s1, v2 :: v_dual_mul_f32 v3, s4, v5
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// GFX11: encoding: [0x01,0x04,0xc6,0xc8,0x04,0x0a,0x02,0x00]
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// SGPR + LITERAL
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v_dual_fmaak_f32 v122, s74, v161, 2.741 :: v_dual_and_b32 v247, v160, v98
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// GFX11: encoding: [0x4a,0x42,0x65,0xc8,0xa0,0xc5,0xf6,0x7a,0x8b,0x6c,0x2f,0x40]
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v_dual_mov_b32 v247, v160 :: v_dual_fmaak_f32 v122, s74, v161, 2.741
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// GFX11: encoding: [0xa0,0x01,0x02,0xca,0x4a,0x42,0x7b,0xf7,0x8b,0x6c,0x2f,0x40]
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// SGPR*2 + LITERAL
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v_dual_fmaak_f32 v122, s74, v161, 2.741 :: v_dual_and_b32 v247, s74, v98
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// GFX11: encoding: [0x4a,0x42,0x65,0xc8,0x4a,0xc4,0xf6,0x7a,0x8b,0x6c,0x2f,0x40]
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// SGPR + LITERAL*2
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v_dual_fmaak_f32 v122, s74, v161, 2.741 :: v_dual_fmamk_f32 v3, v6, 2.741, v1
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// GFX11: encoding: [0x4a,0x42,0x45,0xc8,0x06,0x03,0x02,0x7a,0x8b,0x6c,0x2f,0x40]
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// SGPR*2 + LITERAL*2
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v_dual_fmaak_f32 v122, s74, v161, 2.741 :: v_dual_fmamk_f32 v3, s74, 2.741, v1
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// GFX11: encoding: [0x4a,0x42,0x45,0xc8,0x4a,0x02,0x02,0x7a,0x8b,0x6c,0x2f,0x40]
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// LITERAL + VCC
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v_dual_fmaak_f32 v122, v0, v161, 2.741 :: v_dual_cndmask_b32 v1, v2, v3
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// GFX11: encoding: [0x00,0x43,0x53,0xc8,0x02,0x07,0x00,0x7a,0x8b,0x6c,0x2f,0x40]
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// LITERAL*2 + VCC
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v_dual_fmaak_f32 v122, v0, v161, 2.741 :: v_dual_cndmask_b32 v1, 2.741, v3
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// GFX11: encoding: [0x00,0x43,0x53,0xc8,0xff,0x06,0x00,0x7a,0x8b,0x6c,0x2f,0x40]
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// LITERAL*2 + VCC*2
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v_dual_cndmask_b32 v255, 0xbabe, v2 :: v_dual_cndmask_b32 v6, 0xbabe, v3
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// GFX11: encoding: [0xff,0x04,0x52,0xca,0xff,0x06,0x06,0xff,0xbe,0xba,0x00,0x00]
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// SGPR*2 + VCC
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v_dual_add_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
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// GFX11: encoding: [0x69,0x04,0x12,0xc9,0x69,0x06,0x06,0xff]
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// SGPR*2 + VCC*2
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v_dual_cndmask_b32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
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// GFX11: encoding: [0x01,0x04,0x52,0xca,0x01,0x06,0x06,0xff]
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// VCC*2
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v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, v1, v3
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// GFX11: encoding: [0x6a,0x04,0x12,0xc9,0x01,0x07,0x06,0xff]
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