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Add correct Thumb2 encodings for mvn and friends. 

llvm-svn: 119170
This commit is contained in:
Owen Anderson 2010-11-15 18:45:17 +00:00
parent 56f3a4c761
commit 0e7d728327
2 changed files with 89 additions and 11 deletions
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91
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -170,20 +170,89 @@ def t2addrmode_so_reg : Operand<i32>,
// Multiclass helpers... // Multiclass helpers...
// //
class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> { : T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd; bits<4> Rd;
bits<12> imm;
let Inst{11-8} = Rd{3-0};
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
}
class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn; bits<4> Rn;
bits<12> imm; bits<12> imm;
let Inst{11-8} = Rd{3-0}; let Inst{11-8} = Rd{3-0};
let Inst{19-16} = Rn{3-0};
let Inst{26} = imm{11}; let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8}; let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0}; let Inst{7-0} = imm{7-0};
} }
class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<12> ShiftedRm;
let Inst{11-8} = Rd{3-0};
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
let Inst{7-6} = ShiftedRm{8-7};
}
class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<12> ShiftedRm;
let Inst{11-8} = Rd{3-0};
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
let Inst{7-6} = ShiftedRm{8-7};
}
class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rm;
let Inst{11-8} = Rd{3-0};
let Inst{3-0} = Rm{3-0};
}
class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rm;
let Inst{11-8} = Rd{3-0};
let Inst{3-0} = Rm{3-0};
}
class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rm;
let Inst{11-8} = Rd{3-0};
let Inst{3-0} = Rm{3-0};
}
class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin, class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> { : T2sI<oops, iops, itin, opc, asm, pattern> {
@ -259,9 +328,9 @@ multiclass T2I_un_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
PatFrag opnode, bit Cheap = 0, bit ReMat = 0> { PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
// shifted imm // shifted imm
def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), iii, def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
opc, "\t$dst, $src", opc, "\t$Rd, $imm",
[(set rGPR:$dst, (opnode t2_so_imm:$src))]> { [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
let isAsCheapAsAMove = Cheap; let isAsCheapAsAMove = Cheap;
let isReMaterializable = ReMat; let isReMaterializable = ReMat;
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
@ -272,9 +341,9 @@ multiclass T2I_un_irs<bits<4> opcod, string opc,
let Inst{15} = 0; let Inst{15} = 0;
} }
// register // register
def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), iir, def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
opc, ".w\t$dst, $src", opc, ".w\t$Rd, $Rm",
[(set rGPR:$dst, (opnode rGPR:$src))]> { [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@ -285,9 +354,9 @@ multiclass T2I_un_irs<bits<4> opcod, string opc,
let Inst{5-4} = 0b00; // type let Inst{5-4} = 0b00; // type
} }
// shifted register // shifted register
def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), iis, def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
opc, ".w\t$dst, $src", opc, ".w\t$Rd, $ShiftedRm",
[(set rGPR:$dst, (opnode t2_so_reg:$src))]> { [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;

9
llvm/test/MC/ARM/thumb2.s
View File

@ -12,3 +12,12 @@
adc r1, r1, #1448498774 adc r1, r1, #1448498774
@ CHECK: adc r1, r1, #66846720 @ encoding: [0x7f,0x71,0x41,0xf1] @ CHECK: adc r1, r1, #66846720 @ encoding: [0x7f,0x71,0x41,0xf1]
adc r1, r1, #66846720 adc r1, r1, #66846720
@ CHECK: mvn r0, #187 @ encoding: [0xbb,0x00,0x6f,0xf0]
mvn r0, #187
@ CHECK: mvn r0, #11141290 @ encoding: [0xaa,0x10,0x6f,0xf0]
mvn r0, #11141290
@ CHECK: mvn r0, #-872363008 @ encoding: [0xcc,0x20,0x6f,0xf0]
mvn r0, #-872363008
@ CHECK: mvn r0, #1114112 @ encoding: [0x88,0x10,0x6f,0xf4]
mvn r0, #1114112