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//===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements NewValueJump pass in Hexagon.
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// Ideally, we should merge this as a Peephole pass prior to register
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// allocation, but becuase we have a spill in between the feeder and new value
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// jump instructions, we are forced to write after register allocation.
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// Having said that, we should re-attempt to pull this ealier at some piont
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// in future.
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// The basic approach looks for sequence of predicated jump, compare instruciton
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// that genereates the predicate and, the feeder to the predicate. Once it finds
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// all, it collapses compare and jump instruction into a new valu jump
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// intstructions.
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//
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "hexagon-nvj"
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#include "llvm/PassSupport.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "Hexagon.h"
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#include "HexagonTargetMachine.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonMachineFunctionInfo.h"
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#include <map>
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#include <iostream>
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
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cl::opt<int> DebugHexagonNewValueJump("debug-nvj", cl::Hidden, cl::desc(""));
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static cl::opt<int>
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DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
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"Maximum number of predicated jumps to be converted to New Value Jump"));
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static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
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cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable New Value Jumps"));
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namespace {
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struct HexagonNewValueJump : public MachineFunctionPass {
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const HexagonInstrInfo *QII;
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const HexagonRegisterInfo *QRI;
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public:
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static char ID;
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HexagonNewValueJump() : MachineFunctionPass(ID) { }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const char *getPassName() const {
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return "Hexagon NewValueJump";
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}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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private:
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};
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} // end of anonymous namespace
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char HexagonNewValueJump::ID = 0;
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// We have identified this II could be feeder to NVJ,
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// verify that it can be.
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static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
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const TargetRegisterInfo *TRI,
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MachineBasicBlock::iterator II,
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MachineBasicBlock::iterator end,
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MachineBasicBlock::iterator skip,
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MachineFunction &MF) {
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// Predicated instruction can not be feeder to NVJ.
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if (QII->isPredicated(II))
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return false;
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// Bail out if feederReg is a paired register (double regs in
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// our case). One would think that we can check to see if a given
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// register cmpReg1 or cmpReg2 is a sub register of feederReg
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// using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
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// before the callsite of this function
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// But we can not as it comes in the following fashion.
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// %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
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// %R0<def> = KILL %R0, %D0<imp-use,kill>
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// %P0<def> = CMPEQri %R0<kill>, 0
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// Hence, we need to check if it's a KILL instruction.
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if (II->getOpcode() == TargetOpcode::KILL)
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return false;
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// Make sure there there is no 'def' or 'use' of any of the uses of
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// feeder insn between it's definition, this MI and jump, jmpInst
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// skipping compare, cmpInst.
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// Here's the example.
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// r21=memub(r22+r24<<#0)
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// p0 = cmp.eq(r21, #0)
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// r4=memub(r3+r21<<#0)
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// if (p0.new) jump:t .LBB29_45
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// Without this check, it will be converted into
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// r4=memub(r3+r21<<#0)
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// r21=memub(r22+r24<<#0)
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// p0 = cmp.eq(r21, #0)
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// if (p0.new) jump:t .LBB29_45
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// and result WAR hazards if converted to New Value Jump.
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for (unsigned i = 0; i < II->getNumOperands(); ++i) {
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if (II->getOperand(i).isReg() &&
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(II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
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MachineBasicBlock::iterator localII = II;
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++localII;
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unsigned Reg = II->getOperand(i).getReg();
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for (MachineBasicBlock::iterator localBegin = localII;
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localBegin != end; ++localBegin) {
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if (localBegin == skip ) continue;
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// Check for Subregisters too.
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if (localBegin->modifiesRegister(Reg, TRI) ||
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localBegin->readsRegister(Reg, TRI))
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return false;
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}
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}
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}
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return true;
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}
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// These are the common checks that need to performed
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// to determine if
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// 1. compare instruction can be moved before jump.
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// 2. feeder to the compare instruction can be moved before jump.
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static bool commonChecksToProhibitNewValueJump(bool afterRA,
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MachineBasicBlock::iterator MII) {
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// If store in path, bail out.
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if (MII->getDesc().mayStore())
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return false;
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// if call in path, bail out.
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if (MII->getOpcode() == Hexagon::CALLv3)
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return false;
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// if NVJ is running prior to RA, do the following checks.
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if (!afterRA) {
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// The following Target Opcode instructions are spurious
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// to new value jump. If they are in the path, bail out.
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// KILL sets kill flag on the opcode. It also sets up a
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// single register, out of pair.
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// %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
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// %R0<def> = KILL %R0, %D0<imp-use,kill>
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// %P0<def> = CMPEQri %R0<kill>, 0
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// PHI can be anything after RA.
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// COPY can remateriaze things in between feeder, compare and nvj.
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if (MII->getOpcode() == TargetOpcode::KILL ||
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MII->getOpcode() == TargetOpcode::PHI ||
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MII->getOpcode() == TargetOpcode::COPY)
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return false;
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// The following pseudo Hexagon instructions sets "use" and "def"
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// of registers by individual passes in the backend. At this time,
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// we don't know the scope of usage and definitions of these
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// instructions.
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if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
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MII->getOpcode() == Hexagon::TFR_condset_ii ||
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MII->getOpcode() == Hexagon::TFR_condset_ri ||
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MII->getOpcode() == Hexagon::TFR_condset_ir ||
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MII->getOpcode() == Hexagon::LDriw_pred ||
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MII->getOpcode() == Hexagon::STriw_pred)
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return false;
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}
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return true;
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}
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static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
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const TargetRegisterInfo *TRI,
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MachineBasicBlock::iterator II,
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unsigned pReg,
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bool secondReg,
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bool optLocation,
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MachineBasicBlock::iterator end,
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MachineFunction &MF) {
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MachineInstr *MI = II;
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// If the second operand of the compare is an imm, make sure it's in the
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// range specified by the arch.
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if (!secondReg) {
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int64_t v = MI->getOperand(2).getImm();
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if (MI->getOpcode() == Hexagon::CMPGEri ||
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(MI->getOpcode() == Hexagon::CMPGEUri && v > 0))
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--v;
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if (!(isUInt<5>(v) ||
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((MI->getOpcode() == Hexagon::CMPEQri ||
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MI->getOpcode() == Hexagon::CMPGTri ||
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MI->getOpcode() == Hexagon::CMPGEri) &&
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(v == -1))))
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return false;
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}
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unsigned cmpReg1, cmpOp2;
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cmpReg1 = MI->getOperand(1).getReg();
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if (secondReg) {
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cmpOp2 = MI->getOperand(2).getReg();
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// Make sure that that second register is not from COPY
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// At machine code level, we don't need this, but if we decide
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// to move new value jump prior to RA, we would be needing this.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
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MachineInstr *def = MRI.getVRegDef(cmpOp2);
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if (def->getOpcode() == TargetOpcode::COPY)
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return false;
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}
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}
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// Walk the instructions after the compare (predicate def) to the jump,
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// and satisfy the following conditions.
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++II ;
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for (MachineBasicBlock::iterator localII = II; localII != end;
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++localII) {
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// Check 1.
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// If "common" checks fail, bail out.
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if (!commonChecksToProhibitNewValueJump(optLocation, localII))
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return false;
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// Check 2.
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// If there is a def or use of predicate (result of compare), bail out.
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if (localII->modifiesRegister(pReg, TRI) ||
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localII->readsRegister(pReg, TRI))
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return false;
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// Check 3.
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// If there is a def of any of the use of the compare (operands of compare),
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// bail out.
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// Eg.
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// p0 = cmp.eq(r2, r0)
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// r2 = r4
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// if (p0.new) jump:t .LBB28_3
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if (localII->modifiesRegister(cmpReg1, TRI) ||
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(secondReg && localII->modifiesRegister(cmpOp2, TRI)))
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return false;
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}
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return true;
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}
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// Given a compare operator, return a matching New Value Jump
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// compare operator. Make sure that MI here is included in
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// HexagonInstrInfo.cpp::isNewValueJumpCandidate
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static unsigned getNewValueJumpOpcode(const MachineInstr *MI, int reg,
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bool secondRegNewified) {
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switch (MI->getOpcode()) {
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case Hexagon::CMPEQrr:
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return Hexagon::JMP_EQrrPt_nv_V4;
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case Hexagon::CMPEQri: {
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if (reg >= 0)
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return Hexagon::JMP_EQriPt_nv_V4;
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else
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return Hexagon::JMP_EQriPtneg_nv_V4;
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}
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case Hexagon::CMPLTrr:
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case Hexagon::CMPGTrr: {
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if (secondRegNewified)
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return Hexagon::JMP_GTrrdnPt_nv_V4;
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else
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return Hexagon::JMP_GTrrPt_nv_V4;
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}
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case Hexagon::CMPGEri: {
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if (reg >= 1)
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return Hexagon::JMP_GTriPt_nv_V4;
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else
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return Hexagon::JMP_GTriPtneg_nv_V4;
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}
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case Hexagon::CMPGTri: {
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if (reg >= 0)
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return Hexagon::JMP_GTriPt_nv_V4;
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else
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return Hexagon::JMP_GTriPtneg_nv_V4;
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}
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case Hexagon::CMPLTUrr:
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case Hexagon::CMPGTUrr: {
|
|
|
|
|
if (secondRegNewified)
|
|
|
|
|
return Hexagon::JMP_GTUrrdnPt_nv_V4;
|
|
|
|
|
else
|
|
|
|
|
return Hexagon::JMP_GTUrrPt_nv_V4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case Hexagon::CMPGTUri:
|
|
|
|
|
return Hexagon::JMP_GTUriPt_nv_V4;
|
|
|
|
|
|
|
|
|
|
case Hexagon::CMPGEUri: {
|
|
|
|
|
if (reg == 0)
|
|
|
|
|
return Hexagon::JMP_EQrrPt_nv_V4;
|
|
|
|
|
else
|
|
|
|
|
return Hexagon::JMP_GTUriPt_nv_V4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
llvm_unreachable("Could not find matching New Value Jump instruction.");
|
|
|
|
|
}
|
|
|
|
|
// return *some value* to avoid compiler warning
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
|
|
|
|
|
|
DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
|
|
|
|
|
<< "********** Function: "
|
|
|
|
|
<< MF.getFunction()->getName() << "\n");
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
// for now disable this, if we move NewValueJump before register
|
|
|
|
|
// allocation we need this information.
|
|
|
|
|
LiveVariables &LVs = getAnalysis<LiveVariables>();
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
|
|
|
|
|
QRI =
|
|
|
|
|
static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
|
|
|
|
|
|
|
|
|
|
if (!QRI->Subtarget.hasV4TOps() ||
|
|
|
|
|
DisableNewValueJumps) {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int nvjCount = DbgNVJCount;
|
|
|
|
|
int nvjGenerated = 0;
|
|
|
|
|
|
|
|
|
|
// Loop through all the bb's of the function
|
|
|
|
|
for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
|
|
|
|
|
MBBb != MBBe; ++MBBb) {
|
|
|
|
|
MachineBasicBlock* MBB = MBBb;
|
|
|
|
|
|
|
|
|
|
DEBUG(dbgs() << "** dumping bb ** "
|
|
|
|
|
<< MBB->getNumber() << "\n");
|
|
|
|
|
DEBUG(MBB->dump());
|
|
|
|
|
DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
|
|
|
|
|
bool foundJump = false;
|
|
|
|
|
bool foundCompare = false;
|
|
|
|
|
bool invertPredicate = false;
|
|
|
|
|
unsigned predReg = 0; // predicate reg of the jump.
|
|
|
|
|
unsigned cmpReg1 = 0;
|
|
|
|
|
int cmpOp2 = 0;
|
|
|
|
|
bool MO1IsKill = false;
|
|
|
|
|
bool MO2IsKill = false;
|
|
|
|
|
MachineBasicBlock::iterator jmpPos;
|
|
|
|
|
MachineBasicBlock::iterator cmpPos;
|
|
|
|
|
MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
|
|
|
|
|
MachineBasicBlock *jmpTarget = NULL;
|
|
|
|
|
bool afterRA = false;
|
|
|
|
|
bool isSecondOpReg = false;
|
|
|
|
|
bool isSecondOpNewified = false;
|
|
|
|
|
// Traverse the basic block - bottom up
|
|
|
|
|
for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
|
|
|
|
|
MII != E;) {
|
|
|
|
|
MachineInstr *MI = --MII;
|
|
|
|
|
if (MI->isDebugValue()) {
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
|
|
|
|
|
|
|
|
|
|
if (!foundJump &&
|
|
|
|
|
(MI->getOpcode() == Hexagon::JMP_c ||
|
|
|
|
|
MI->getOpcode() == Hexagon::JMP_cNot ||
|
|
|
|
|
MI->getOpcode() == Hexagon::JMP_cdnPt ||
|
|
|
|
|
MI->getOpcode() == Hexagon::JMP_cdnPnt ||
|
|
|
|
|
MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
|
|
|
|
|
MI->getOpcode() == Hexagon::JMP_cdnNotPnt)) {
|
|
|
|
|
// This is where you would insert your compare and
|
|
|
|
|
// instr that feeds compare
|
|
|
|
|
jmpPos = MII;
|
|
|
|
|
jmpInstr = MI;
|
|
|
|
|
predReg = MI->getOperand(0).getReg();
|
|
|
|
|
afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
|
|
|
|
|
|
|
|
|
|
// If ifconverter had not messed up with the kill flags of the
|
|
|
|
|
// operands, the following check on the kill flag would suffice.
|
|
|
|
|
// if(!jmpInstr->getOperand(0).isKill()) break;
|
|
|
|
|
|
|
|
|
|
// This predicate register is live out out of BB
|
|
|
|
|
// this would only work if we can actually use Live
|
|
|
|
|
// variable analysis on phy regs - but LLVM does not
|
|
|
|
|
// provide LV analysis on phys regs.
|
|
|
|
|
//if(LVs.isLiveOut(predReg, *MBB)) break;
|
|
|
|
|
|
|
|
|
|
// Get all the successors of this block - which will always
|
|
|
|
|
// be 2. Check if the predicate register is live in in those
|
|
|
|
|
// successor. If yes, we can not delete the predicate -
|
|
|
|
|
// I am doing this only because LLVM does not provide LiveOut
|
|
|
|
|
// at the BB level.
|
|
|
|
|
bool predLive = false;
|
|
|
|
|
for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
|
|
|
|
|
SIE = MBB->succ_end(); SI != SIE; ++SI) {
|
|
|
|
|
MachineBasicBlock* succMBB = *SI;
|
|
|
|
|
if (succMBB->isLiveIn(predReg)) {
|
|
|
|
|
predLive = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (predLive)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
jmpTarget = MI->getOperand(1).getMBB();
|
|
|
|
|
foundJump = true;
|
|
|
|
|
if (MI->getOpcode() == Hexagon::JMP_cNot ||
|
|
|
|
|
MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
|
|
|
|
|
MI->getOpcode() == Hexagon::JMP_cdnNotPnt) {
|
|
|
|
|
invertPredicate = true;
|
|
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// No new value jump if there is a barrier. A barrier has to be in its
|
|
|
|
|
// own packet. A barrier has zero operands. We conservatively bail out
|
|
|
|
|
// here if we see any instruction with zero operands.
|
|
|
|
|
if (foundJump && MI->getNumOperands() == 0)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
if (foundJump &&
|
|
|
|
|
!foundCompare &&
|
|
|
|
|
MI->getOperand(0).isReg() &&
|
|
|
|
|
MI->getOperand(0).getReg() == predReg) {
|
|
|
|
|
|
|
|
|
|
// Not all compares can be new value compare. Arch Spec: 7.6.1.1
|
|
|
|
|
if (QII->isNewValueJumpCandidate(MI)) {
|
|
|
|
|
|
|
|
|
|
assert((MI->getDesc().isCompare()) &&
|
|
|
|
|
"Only compare instruction can be collapsed into New Value Jump");
|
|
|
|
|
isSecondOpReg = MI->getOperand(2).isReg();
|
|
|
|
|
|
|
|
|
|
if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
|
|
|
|
|
afterRA, jmpPos, MF))
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
cmpInstr = MI;
|
|
|
|
|
cmpPos = MII;
|
|
|
|
|
foundCompare = true;
|
|
|
|
|
|
|
|
|
|
// We need cmpReg1 and cmpOp2(imm or reg) while building
|
|
|
|
|
// new value jump instruction.
|
|
|
|
|
cmpReg1 = MI->getOperand(1).getReg();
|
|
|
|
|
if (MI->getOperand(1).isKill())
|
|
|
|
|
MO1IsKill = true;
|
|
|
|
|
|
|
|
|
|
if (isSecondOpReg) {
|
|
|
|
|
cmpOp2 = MI->getOperand(2).getReg();
|
|
|
|
|
if (MI->getOperand(2).isKill())
|
|
|
|
|
MO2IsKill = true;
|
|
|
|
|
} else
|
|
|
|
|
cmpOp2 = MI->getOperand(2).getImm();
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (foundCompare && foundJump) {
|
|
|
|
|
|
|
|
|
|
// If "common" checks fail, bail out on this BB.
|
|
|
|
|
if (!commonChecksToProhibitNewValueJump(afterRA, MII))
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
bool foundFeeder = false;
|
|
|
|
|
MachineBasicBlock::iterator feederPos = MII;
|
|
|
|
|
if (MI->getOperand(0).isReg() &&
|
|
|
|
|
MI->getOperand(0).isDef() &&
|
|
|
|
|
(MI->getOperand(0).getReg() == cmpReg1 ||
|
|
|
|
|
(isSecondOpReg &&
|
|
|
|
|
MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
|
|
|
|
|
|
|
|
|
|
unsigned feederReg = MI->getOperand(0).getReg();
|
|
|
|
|
|
|
|
|
|
// First try to see if we can get the feeder from the first operand
|
|
|
|
|
// of the compare. If we can not, and if secondOpReg is true
|
|
|
|
|
// (second operand of the compare is also register), try that one.
|
|
|
|
|
// TODO: Try to come up with some heuristic to figure out which
|
|
|
|
|
// feeder would benefit.
|
|
|
|
|
|
|
|
|
|
if (feederReg == cmpReg1) {
|
|
|
|
|
if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
|
|
|
|
|
if (!isSecondOpReg)
|
|
|
|
|
break;
|
|
|
|
|
else
|
|
|
|
|
continue;
|
|
|
|
|
} else
|
|
|
|
|
foundFeeder = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!foundFeeder &&
|
|
|
|
|
isSecondOpReg &&
|
|
|
|
|
feederReg == (unsigned) cmpOp2)
|
|
|
|
|
if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
if (isSecondOpReg) {
|
|
|
|
|
// In case of CMPLT, or CMPLTU, or EQ with the second register
|
|
|
|
|
// to newify, swap the operands.
|
|
|
|
|
if (cmpInstr->getOpcode() == Hexagon::CMPLTrr ||
|
|
|
|
|
cmpInstr->getOpcode() == Hexagon::CMPLTUrr ||
|
|
|
|
|
(cmpInstr->getOpcode() == Hexagon::CMPEQrr &&
|
|
|
|
|
feederReg == (unsigned) cmpOp2)) {
|
|
|
|
|
unsigned tmp = cmpReg1;
|
|
|
|
|
bool tmpIsKill = MO1IsKill;
|
|
|
|
|
cmpReg1 = cmpOp2;
|
|
|
|
|
MO1IsKill = MO2IsKill;
|
|
|
|
|
cmpOp2 = tmp;
|
|
|
|
|
MO2IsKill = tmpIsKill;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Now we have swapped the operands, all we need to check is,
|
|
|
|
|
// if the second operand (after swap) is the feeder.
|
|
|
|
|
// And if it is, make a note.
|
|
|
|
|
if (feederReg == (unsigned)cmpOp2)
|
|
|
|
|
isSecondOpNewified = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Now that we are moving feeder close the jump,
|
|
|
|
|
// make sure we are respecting the kill values of
|
|
|
|
|
// the operands of the feeder.
|
|
|
|
|
|
|
|
|
|
bool updatedIsKill = false;
|
|
|
|
|
for (unsigned i = 0; i < MI->getNumOperands(); i++) {
|
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
|
if (MO.isReg() && MO.isUse()) {
|
|
|
|
|
unsigned feederReg = MO.getReg();
|
|
|
|
|
for (MachineBasicBlock::iterator localII = feederPos,
|
|
|
|
|
end = jmpPos; localII != end; localII++) {
|
|
|
|
|
MachineInstr *localMI = localII;
|
|
|
|
|
for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
|
|
|
|
|
MachineOperand &localMO = localMI->getOperand(j);
|
|
|
|
|
if (localMO.isReg() && localMO.isUse() &&
|
|
|
|
|
localMO.isKill() && feederReg == localMO.getReg()) {
|
|
|
|
|
// We found that there is kill of a use register
|
|
|
|
|
// Set up a kill flag on the register
|
|
|
|
|
localMO.setIsKill(false);
|
|
|
|
|
MO.setIsKill();
|
|
|
|
|
updatedIsKill = true;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (updatedIsKill) break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (updatedIsKill) break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
MBB->splice(jmpPos, MI->getParent(), MI);
|
|
|
|
|
MBB->splice(jmpPos, MI->getParent(), cmpInstr);
|
|
|
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
|
|
|
MachineInstr *NewMI;
|
|
|
|
|
|
|
|
|
|
assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
|
|
|
|
|
"This compare is not a New Value Jump candidate.");
|
|
|
|
|
unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
|
|
|
|
|
isSecondOpNewified);
|
|
|
|
|
if (invertPredicate)
|
|
|
|
|
opc = QII->getInvertedPredicatedOpcode(opc);
|
|
|
|
|
|
|
|
|
|
// Manage the conversions from CMPGEUri to either CMPEQrr
|
|
|
|
|
// or CMPGTUri properly. See Arch spec for CMPGEUri instructions.
|
|
|
|
|
// This has to be after the getNewValueJumpOpcode function call as
|
|
|
|
|
// second operand of the compare could be modified in this logic.
|
|
|
|
|
if (cmpInstr->getOpcode() == Hexagon::CMPGEUri) {
|
|
|
|
|
if (cmpOp2 == 0) {
|
|
|
|
|
cmpOp2 = cmpReg1;
|
|
|
|
|
MO2IsKill = MO1IsKill;
|
|
|
|
|
isSecondOpReg = true;
|
|
|
|
|
} else
|
|
|
|
|
--cmpOp2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Manage the conversions from CMPGEri to CMPGTUri properly.
|
|
|
|
|
// See Arch spec for CMPGEri instructions.
|
|
|
|
|
if (cmpInstr->getOpcode() == Hexagon::CMPGEri)
|
|
|
|
|
--cmpOp2;
|
|
|
|
|
|
|
|
|
|
if (isSecondOpReg) {
|
|
|
|
|
NewMI = BuildMI(*MBB, jmpPos, dl,
|
|
|
|
|
QII->get(opc))
|
|
|
|
|
.addReg(cmpReg1, getKillRegState(MO1IsKill))
|
|
|
|
|
.addReg(cmpOp2, getKillRegState(MO2IsKill))
|
|
|
|
|
.addMBB(jmpTarget);
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
NewMI = BuildMI(*MBB, jmpPos, dl,
|
|
|
|
|
QII->get(opc))
|
|
|
|
|
.addReg(cmpReg1, getKillRegState(MO1IsKill))
|
|
|
|
|
.addImm(cmpOp2)
|
|
|
|
|
.addMBB(jmpTarget);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
assert(NewMI && "New Value Jump Instruction Not created!");
|
|
|
|
|
if (cmpInstr->getOperand(0).isReg() &&
|
|
|
|
|
cmpInstr->getOperand(0).isKill())
|
|
|
|
|
cmpInstr->getOperand(0).setIsKill(false);
|
|
|
|
|
if (cmpInstr->getOperand(1).isReg() &&
|
|
|
|
|
cmpInstr->getOperand(1).isKill())
|
|
|
|
|
cmpInstr->getOperand(1).setIsKill(false);
|
|
|
|
|
cmpInstr->eraseFromParent();
|
|
|
|
|
jmpInstr->eraseFromParent();
|
|
|
|
|
++nvjGenerated;
|
|
|
|
|
++NumNVJGenerated;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
FunctionPass *llvm::createHexagonNewValueJump() {
|
|
|
|
|
return new HexagonNewValueJump();
|
|
|
|
|
}
|
Sirish Pande