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Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target. 

llvm-svn: 77174
This commit is contained in:
Evan Cheng 2009-07-27 00:24:36 +00:00
parent 26b51b15ed
commit 0e5b149930
3 changed files with 23 additions and 49 deletions
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35
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -491,6 +491,7 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
SrcSubIdx = DstSubIdx = 0; // No sub-registers. SrcSubIdx = DstSubIdx = 0; // No sub-registers.
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: break;
case ARM::FCPYS: case ARM::FCPYS:
case ARM::FCPYD: case ARM::FCPYD:
case ARM::VMOVD: case ARM::VMOVD:
@ -521,8 +522,10 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned unsigned
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const { int &FrameIndex) const {
unsigned oc = MI->getOpcode(); switch (MI->getOpcode()) {
if (oc == getOpcode(ARMII::LDRrr)) { default: break;
case ARM::LDR:
case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
if (MI->getOperand(1).isFI() && if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() && MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() && MI->getOperand(3).isImm() &&
@ -531,22 +534,25 @@ ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
FrameIndex = MI->getOperand(1).getIndex(); FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg(); return MI->getOperand(0).getReg();
} }
} break;
else if (oc == getOpcode(ARMII::LDRri)) { case ARM::t2LDRi12:
case ARM::tRestore:
if (MI->getOperand(1).isFI() && if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) { MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex(); FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg(); return MI->getOperand(0).getReg();
} }
} break;
else if (oc == ARM::FLDD || oc == ARM::FLDS) { case ARM::FLDD:
case ARM::FLDS:
if (MI->getOperand(1).isFI() && if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) { MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex(); FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg(); return MI->getOperand(0).getReg();
} }
break;
} }
return 0; return 0;
@ -555,8 +561,10 @@ ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
unsigned unsigned
ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const { int &FrameIndex) const {
unsigned oc = MI->getOpcode(); switch (MI->getOpcode()) {
if (oc == getOpcode(ARMII::STRrr)) { default: break;
case ARM::STR:
case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
if (MI->getOperand(1).isFI() && if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() && MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() && MI->getOperand(3).isImm() &&
@ -565,22 +573,25 @@ ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
FrameIndex = MI->getOperand(1).getIndex(); FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg(); return MI->getOperand(0).getReg();
} }
} break;
else if (oc == getOpcode(ARMII::STRri)) { case ARM::t2STRi12:
case ARM::tSpill:
if (MI->getOperand(1).isFI() && if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) { MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex(); FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg(); return MI->getOperand(0).getReg();
} }
} break;
else if (oc == ARM::FSTD || oc == ARM::FSTS) { case ARM::FSTD:
case ARM::FSTS:
if (MI->getOperand(1).isFI() && if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) { MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex(); FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg(); return MI->getOperand(0).getReg();
} }
break;
} }
return 0; return 0;

32
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
View File

@ -71,38 +71,6 @@ Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
return false; return false;
} }
unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {
default: break;
case ARM::tRestore:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
}
return 0;
}
unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {
default: break;
case ARM::tSpill:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
}
return 0;
}
bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB, bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,

5
llvm/lib/Target/ARM/Thumb1InstrInfo.h
View File

@ -50,11 +50,6 @@ public:
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const; const std::vector<CalleeSavedInfo> &CSI) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
bool copyRegToReg(MachineBasicBlock &MBB, bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,