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Add MOVi ARM encoding. 

llvm-svn: 116321
This commit is contained in:
Jim Grosbach 2010-10-12 18:09:12 +00:00
parent f220088295
commit 0e57a9f7a9
2 changed files with 24 additions and 14 deletions
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31
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -1513,40 +1513,43 @@ def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
//
let neverHasSideEffects = 1 in
def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
"mov", "\t$dst, $src", []>, UnaryDP {
bits<4> dst;
bits<4> src;
def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
"mov", "\t$Rd, $Rm", []>, UnaryDP {
bits<4> Rd;
bits<4> Rm;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let Inst{3-0} = src;
let Inst{15-12} = dst;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
}
// A version for the smaller set of tail call registers.
let neverHasSideEffects = 1 in
def MOVr_TC : AsI1<0b1101, (outs tcGPR:$dst), (ins tcGPR:$src), DPFrm,
IIC_iMOVr, "mov", "\t$dst, $src", []>, UnaryDP {
bits<4> dst;
bits<4> src;
def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
bits<4> Rd;
bits<4> Rm;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let Inst{3-0} = src;
let Inst{15-12} = dst;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
}
def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins so_reg:$src),
DPSoRegFrm, IIC_iMOVsr,
"mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
"mov", "\t$Rd, $src", [(set GPR:$Rd, so_reg:$src)]>, UnaryDP {
let Inst{25} = 0;
}
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
"mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
bits<4> Rd;
let Inst{25} = 1;
let Inst{15-12} = Rd;
let Inst{19-16} = 0b0000;
}
let isReMaterializable = 1, isAsCheapAsAMove = 1 in

7
llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -150,6 +150,13 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
unsigned Value = getBinaryCodeForInstr(MI);
switch (Opcode) {
default: break;
case ARM::MOVi:
// The 's' bit.
if (MI.getOperand(4).getReg() == ARM::CPSR)
Value |= 1 << ARMII::S_BitShift;
// The shifted immediate value.
Value |= getMachineSoImmOpValue((unsigned)MI.getOperand(1).getImm());
break;
case ARM::ADDri:
case ARM::ANDri:
case ARM::BICri: